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verilog: don't destroy() when module changes

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This commit is contained in:
Steven Hugg 2019-04-22 10:09:33 -04:00
parent d8016ff718
commit 8af1c5d3c5
4 changed files with 1367 additions and 6 deletions
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1365
presets/verilog/cpu6502.v Normal file
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File diff suppressed because it is too large Load Diff

2
scripts/sync-version-prod.sh
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@ -19,8 +19,6 @@ echo "Extracting to $TMPDIR..."
rm -fr $TMPDIR
mkdir -p $TMPDIR
git archive $VERSION | tar x -C $TMPDIR
ls $TMPDIR
pause
echo "Copying to $DESTPATH..."
rsync --stats --exclude '.*' --exclude 'scripts/*' --exclude=node_modules --copy-dest=$DEVPATH -rilz --chmod=a+rx -e "ssh -p 2222" $TMPDIR/ $SUBMODS $DESTPATH
rsync --stats -rpilvz --chmod=a+rx -e "ssh -p 2222" --copy-dest=$DEVPATH ./gen $DESTPATH/

4
src/platform/verilog.ts
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@ -625,10 +625,8 @@ var VerilogPlatform = function(mainElement, options) {
}
// restart audio
this.restartAudio();
// destroy scope
if (this.waveview) {
this.waveview.destroy();
this.waveview = null;
this.waveview.recreate();
}
}

2
tss

@ -1 +1 @@
Subproject commit 61a1691a1de05dca3b694bf603db49ffbaf572cf
Subproject commit 5b5ee67fc06956bc7dce51726e98812d2d897eaa