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verilog: don't destroy() when module changes
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parent
d8016ff718
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1365
presets/verilog/cpu6502.v
Normal file
1365
presets/verilog/cpu6502.v
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File diff suppressed because it is too large
Load Diff
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@ -19,8 +19,6 @@ echo "Extracting to $TMPDIR..."
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rm -fr $TMPDIR
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rm -fr $TMPDIR
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mkdir -p $TMPDIR
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mkdir -p $TMPDIR
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git archive $VERSION | tar x -C $TMPDIR
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git archive $VERSION | tar x -C $TMPDIR
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ls $TMPDIR
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pause
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echo "Copying to $DESTPATH..."
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echo "Copying to $DESTPATH..."
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rsync --stats --exclude '.*' --exclude 'scripts/*' --exclude=node_modules --copy-dest=$DEVPATH -rilz --chmod=a+rx -e "ssh -p 2222" $TMPDIR/ $SUBMODS $DESTPATH
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rsync --stats --exclude '.*' --exclude 'scripts/*' --exclude=node_modules --copy-dest=$DEVPATH -rilz --chmod=a+rx -e "ssh -p 2222" $TMPDIR/ $SUBMODS $DESTPATH
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rsync --stats -rpilvz --chmod=a+rx -e "ssh -p 2222" --copy-dest=$DEVPATH ./gen $DESTPATH/
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rsync --stats -rpilvz --chmod=a+rx -e "ssh -p 2222" --copy-dest=$DEVPATH ./gen $DESTPATH/
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@ -625,10 +625,8 @@ var VerilogPlatform = function(mainElement, options) {
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}
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}
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// restart audio
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// restart audio
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this.restartAudio();
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this.restartAudio();
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// destroy scope
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if (this.waveview) {
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if (this.waveview) {
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this.waveview.destroy();
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this.waveview.recreate();
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this.waveview = null;
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}
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}
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}
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}
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2
tss
2
tss
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@ -1 +1 @@
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Subproject commit 61a1691a1de05dca3b694bf603db49ffbaf572cf
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Subproject commit 5b5ee67fc06956bc7dce51726e98812d2d897eaa
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