mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2026-04-20 15:16:38 +00:00
updated package-lock.json, define __MAIN__ and __8BITWORKSHOP__ for ca65
This commit is contained in:
Steven Hugg
+5
-29
@@ -16,7 +16,7 @@ global.onmessage({data:{preload:'inform6'}});
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// TODO: check msg against spec
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function compile(tool, code, platform, callback, outlen, nlines, nerrors, options) {
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var msgs = [{code:code, platform:platform, tool:tool, path:'src.'+tool}];
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var msgs = [{code:code, platform:platform, tool:tool, path:'src.'+tool, mainfile:true}];
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doBuild(msgs, callback, outlen, nlines, nerrors, options);
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}
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@@ -87,22 +87,8 @@ describe('Worker', function() {
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it('should NOT assemble DASM', function(done) {
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compile('dasm', '\tprocessor 6502\n\torg $f000 ; this is a comment\nfoo asl a\n', 'vcs', done, 0, 0, 2);
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});
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/*
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it('should assemble ACME', function(done) {
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compile('acme', 'foo: lda #0\n', 'vcs', done, 2, 0); // TODO
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});
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it('should NOT assemble ACME', function(done) {
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compile('acme', 'foo: xxx #0\n', 'vcs', done, 0, 0, 2); // TODO
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});
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it('should compile PLASMA', function(done) {
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compile('plasm', 'word x = 0', 'apple2', done, 5, 0);
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});
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it('should NOT compile PLASMA', function(done) {
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compile('plasm', 'word x = ', 'apple2', done, 0, 0, 1);
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});
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*/
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it('should compile CC65', function(done) {
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compile('cc65', 'int main() {\nint x=1;\nreturn x+2;\n}', 'nes.mame', done, 40976, 3);
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compile('cc65', '#if defined(__8BITWORKSHOP__) && defined(__MAIN__)\nint main() {\nint x=1;\nreturn x+2;\n}\n#endif', 'nes.mame', done, 40976, 3);
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});
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it('should NOT compile CC65 (compile error)', function(done) {
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compile('cc65', 'int main() {\nint x=1;\nprintf("%d",x);\nreturn x+2;\n}', 'nes', done, 0, 0, 1);
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@@ -113,14 +99,6 @@ describe('Worker', function() {
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it('should NOT compile CC65 (preproc error)', function(done) {
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compile('cc65', '#include "NOSUCH.file"\n', 'nes', done, 0, 0, 1, {ignoreErrorPath:true});
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});
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/*
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it('should assemble Z80ASM', function(done) {
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compile('z80asm', '\tMODULE test\n\tEXTERN _puts\n\tld hl,$0000\n\tret\n', 'mw8080bw', done, 4, 2, 0);
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});
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it('should NOT assemble Z80ASM', function(done) {
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compile('z80asm', 'ddwiuweq', 'mw8080bw', done, 0, 0, 1);
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});
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*/
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it('should assemble SDASZ80', function(done) {
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compile('sdasz80', '\tld hl,#0\n\tret\n', 'mw8080bw', done, 8192, 2);
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});
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@@ -131,7 +109,7 @@ describe('Worker', function() {
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compile('sdasz80', '\tcall divxxx\n', 'mw8080bw', done, 0, 0, 1, {ignoreErrorPath:true});
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});
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it('should compile SDCC', function(done) {
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compile('sdcc', 'int foo=0; // comment\nint main(int argc) {\nint x=1;\nint y=2+argc;\nreturn x+y+argc;\n}\n', 'mw8080bw', done, 8192, 3, 0);
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compile('sdcc', 'int foo=0; // comment\n#if defined(__8BITWORKSHOP__) && defined(__MAIN__)\nint main(int argc) {\nint x=1;\nint y=2+argc;\nreturn x+y+argc;\n}\n#endif\n', 'mw8080bw', done, 8192, 3, 0);
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});
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it('should compile SDCC w/ include', function(done) {
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compile('sdcc', '#include <string.h>\nvoid main() {\nstrlen(0);\n}\n', 'mw8080bw', done, 8192, 2, 0);
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@@ -261,18 +239,16 @@ describe('Worker', function() {
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compile('cc65', '#define NES_MAPPER 4\nint main() {\nint x=1;\nreturn x+2;\n}', 'nes', done, 131088, 3);
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});
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it('should assemble CA65', function(done) {
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compile('ca65', ';#define LIBARGS ,\n\t.segment "HEADER"\n\t.segment "STARTUP"\n\t.segment "CHARS"\n\t.segment "VECTORS"\n\t.segment "SAMPLES"\n\t.segment "CODE"\n\tlda #0\n\tsta $1\n', 'nes', done, 131088, 2);
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compile('ca65', ';#define LIBARGS ,\n\t.segment "HEADER"\n\t.segment "STARTUP"\n\t.segment "CHARS"\n\t.segment "VECTORS"\n\t.segment "SAMPLES"\n\t.segment "CODE"\n.ifdef __MAIN__\n\tlda #0\n\tsta $1\n.endif\n', 'nes', done, 131088, 2);
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});
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it('should compile C64 cc65 skeleton', function(done) {
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var csource = ab2str(fs.readFileSync('presets/c64/skeleton.cc65'));
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compile('cc65', csource, 'c64.wasm', done, 2753, 2, 0);
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});
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/*
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it('should compile zmachine inform6 skeleton', function(done) {
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var csource = ab2str(fs.readFileSync('presets/zmachine/skeleton.inform6'));
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compile('inform6', csource, 'hello.z5', done, 2753, 2, 0);
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compile('inform6', csource, 'hello.z5', done, 92672, 0, 0);
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});
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*/
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// TODO: vectrex, x86
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it('should compile basic example', function(done) {
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var csource = ab2str(fs.readFileSync('presets/basic/wumpus.bas'));
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@@ -1,101 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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// verilator lint_off LATCH
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// verilator lint_off UNOPT
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// verilator lint_off UNOPTFLAT
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// verilator lint_off MULTIDRIVEN
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// verilator lint_off BLKANDNBLK
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reg [31:0] comcnt;
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reg [31:0] dlycnt; initial dlycnt=0;
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reg [31:0] lastdlycnt; initial lastdlycnt = 0;
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reg [31:0] comrun; initial comrun = 0;
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reg [31:0] comrunm1;
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reg [31:0] dlyrun; initial dlyrun = 0;
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reg [31:0] dlyrunm1;
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always @ (posedge clk) begin
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$write("[%0t] cyc %d\n",$time,cyc);
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cyc <= cyc + 1;
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if (cyc==2) begin
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// Test # of iters
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lastdlycnt = 0;
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comcnt = 0;
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dlycnt <= 0;
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end
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if (cyc==3) begin
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dlyrun <= 5;
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dlycnt <= 0;
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end
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if (cyc==4) begin
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comrun = 4;
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end
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end
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always @ (negedge clk) begin
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if (cyc==5) begin
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$display("%d %d\n", dlycnt, comcnt);
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if (dlycnt != 32'd5) $stop;
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if (comcnt != 32'd19) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// This forms a "loop" where we keep going through the always till comrun=0
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reg runclk; initial runclk = 1'b0;
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always @ (/*AS*/comrunm1 or dlycnt) begin
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if (lastdlycnt != dlycnt) begin
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comrun = 3;
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$write ("[%0t] comrun=%0d start\n", $time, comrun);
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end
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else if (comrun > 0) begin
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comrun = comrunm1;
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if (comrunm1==1) begin
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runclk = 1;
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$write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun);
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end
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else $write ("[%0t] comrun=%0d\n", $time, comrun);
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end
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lastdlycnt = dlycnt;
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end
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always @ (/*AS*/comrun) begin
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if (comrun!=0) begin
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comrunm1 = comrun - 32'd1;
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comcnt = comcnt + 32'd1;
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$write("[%0t] comcnt=%0d\n",$time,comcnt);
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end
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end
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// This forms a "loop" where we keep going through the always till dlyrun=0
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reg runclkrst;
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always @ (posedge runclk) begin
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runclkrst <= 1;
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$write ("[%0t] runclk\n", $time);
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if (dlyrun > 0) begin
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dlyrun <= dlyrun - 32'd1;
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dlycnt <= dlycnt + 32'd1;
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$write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1);
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end
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end
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always @* begin
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if (runclkrst) begin
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$write ("[%0t] runclk reset\n", $time);
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runclkrst = 0;
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runclk = 0;
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end
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end
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endmodule
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