mirror of
https://github.com/sehugg/8bitworkshop.git
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sync vs async RAM
This commit is contained in:
Steven Hugg
parent
b5c74234f3
commit
8f1563f88e
@ -1,8 +1,59 @@
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`ifndef CPU16_H
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`define CPU16_H
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// include ALU module
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`include "cpu8.v"
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// ALU operations
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`define OP_ZERO 4'h0
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`define OP_LOAD_A 4'h1
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`define OP_INC 4'h2
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`define OP_DEC 4'h3
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`define OP_ASL 4'h4
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`define OP_LSR 4'h5
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`define OP_ROL 4'h6
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`define OP_ROR 4'h7
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`define OP_OR 4'h8
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`define OP_AND 4'h9
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`define OP_XOR 4'ha
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`define OP_LOAD_B 4'hb
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`define OP_ADD 4'hc
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`define OP_SUB 4'hd
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`define OP_ADC 4'he
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`define OP_SBB 4'hf
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module ALU(A, B, Y, aluop, carry);
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parameter N = 8;
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input [N-1:0] A;
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input [N-1:0] B;
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output [N:0] Y;
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input [3:0] aluop;
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input carry;
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always @(*)
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case (aluop)
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// unary operations
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`OP_ZERO: Y = 0;
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`OP_LOAD_A: Y = {1'b0, A};
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`OP_INC: Y = A + 1;
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`OP_DEC: Y = A - 1;
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// unary operations that generate and/or use carry
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`OP_ASL: Y = {A, 1'b0};
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`OP_LSR: Y = {A[0], 1'b0, A[N-1:1]};
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`OP_ROL: Y = {A, carry};
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`OP_ROR: Y = {A[0], carry, A[N-1:1]};
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// binary operations
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`OP_OR: Y = {1'b0, A | B};
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`OP_AND: Y = {1'b0, A & B};
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`OP_XOR: Y = {1'b0, A ^ B};
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`OP_LOAD_B: Y = {1'b0, B};
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// binary operations that generate and/or use carry
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`OP_ADD: Y = A + B;
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`OP_SUB: Y = A - B;
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`OP_ADC: Y = A + B + (carry?1:0);
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`OP_SBB: Y = A - B - (carry?1:0);
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endcase
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endmodule
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/*
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00000aaa 0++++bbb operation A+B->A
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@ -30,6 +81,9 @@ module CPU16(clk, reset, hold, busy,
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output [15:0] data_out;
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output write;
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// wait state for RAM?
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parameter RAM_WAIT = 1;
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reg [15:0] regs[0:7]; // 8 16-bit registers
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reg [2:0] state; // CPU state
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@ -51,6 +105,8 @@ module CPU16(clk, reset, hold, busy,
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localparam S_SELECT = 1;
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localparam S_DECODE = 2;
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localparam S_COMPUTE = 3;
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localparam S_DECODE_WAIT = 4;
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localparam S_COMPUTE_WAIT = 5;
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localparam SP = 6; // stack ptr = register 6
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localparam IP = 7; // IP = register 7
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@ -86,22 +142,22 @@ module CPU16(clk, reset, hold, busy,
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busy <= 0;
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address <= regs[IP];
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regs[IP] <= regs[IP] + 1;
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state <= S_DECODE;
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state <= RAM_WAIT ? S_DECODE_WAIT : S_DECODE;
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end
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end
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// state 2: read/decode opcode
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S_DECODE: begin
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// default next state
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state <= RAM_WAIT && data_in[11] ? S_COMPUTE_WAIT : S_COMPUTE;
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casez (data_in)
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// 00000aaa0++++bbb operation A+B->A
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16'b00000???0???????: begin
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aluop <= data_in[6:3];
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state <= S_COMPUTE;
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end
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// 00001aaa01+++bbb operation A+[B]->A
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16'b00001???01??????: begin
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address <= regs[data_in[2:0]];
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aluop <= data_in[6:3];
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state <= S_COMPUTE;
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if (data_in[2:0] == SP)
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regs[SP] <= regs[SP] + 1;
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end
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@ -110,18 +166,15 @@ module CPU16(clk, reset, hold, busy,
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address <= regs[IP];
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regs[IP] <= regs[IP] + 1;
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aluop <= data_in[6:3];
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state <= S_COMPUTE;
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end
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// 11+++aaa######## immediate binary operation
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16'b11??????????????: begin
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aluop <= data_in[14:11];
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state <= S_COMPUTE;
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end
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// 00101aaa######## load ZP memory
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16'b00101???????????: begin
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address <= {8'b0, data_in[7:0]};
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aluop <= `OP_LOAD_B;
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state <= S_COMPUTE;
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end
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// 00110aaa######## store ZP memory
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16'b00110???????????: begin
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@ -134,7 +187,6 @@ module CPU16(clk, reset, hold, busy,
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16'b01001???????????: begin
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address <= regs[data_in[2:0]] + 16'($signed(data_in[7:3]));
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aluop <= `OP_LOAD_B;
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state <= S_COMPUTE;
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if (data_in[2:0] == SP)
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regs[SP] <= regs[SP] + 1;
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end
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@ -152,11 +204,10 @@ module CPU16(clk, reset, hold, busy,
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address <= regs[IP];
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regs[IP] <= regs[IP] + 1;
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aluop <= data_in[6:3];
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state <= S_COMPUTE;
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end
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// 01110aaa00cccbbb store A -> [B+#], C -> IP
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// 01110aaa00cccbbb store A -> [B], C -> IP
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16'b01110???00??????: begin
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address <= regs[data_in[2:0]] + 16'($signed(data_in[7:3]));
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address <= regs[data_in[2:0]];
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data_out <= regs[data_in[10:8]];
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write <= 1;
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state <= S_SELECT;
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@ -195,6 +246,13 @@ module CPU16(clk, reset, hold, busy,
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// repeat CPU loop
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state <= S_SELECT;
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end
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// wait 1 cycle for RAM read
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S_DECODE_WAIT: begin
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state <= S_DECODE;
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end
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S_COMPUTE_WAIT : begin
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state <= S_COMPUTE;
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end
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endcase
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end
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@ -212,7 +270,8 @@ module test_CPU16_top(
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output [15:0] IP,
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output zero,
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output carry,
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output busy
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output busy,
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output [2:0] state
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);
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reg [15:0] ram[0:65535];
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@ -221,6 +280,7 @@ module test_CPU16_top(
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assign IP = cpu.regs[7];
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assign zero = cpu.zero;
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assign carry = cpu.carry;
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assign state = cpu.state;
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CPU16 cpu(
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.clk(clk),
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@ -237,11 +297,11 @@ module test_CPU16_top(
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ram[address_bus] <= from_cpu;
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end
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always @(*)
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always @(posedge clk)
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if (address_bus[15] == 0)
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to_cpu = ram[address_bus];
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to_cpu <= ram[address_bus];
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else
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to_cpu = rom[address_bus[7:0]];
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to_cpu <= rom[address_bus[7:0]];
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`ifdef EXT_INLINE_ASM
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initial begin
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@ -250,13 +310,13 @@ module test_CPU16_top(
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.arch femto16
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.org 0x8000
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.len 256
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mov sp,@$6fff
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mov dx,@Fib
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jsr dx
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reset
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Fib:
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mov ax,#1
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mov bx,#0
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mov sp,@$6fff
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Loop:
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mov cx,ax
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add ax,bx
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@ -5,7 +5,6 @@
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`include "sprite_scanline_renderer.v"
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`include "lfsr.v"
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`include "sound_generator.v"
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`include "cpu8.v"
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`include "cpu16.v"
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module maze_game_top(clk, reset, hsync, vsync, rgb);
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@ -19,14 +18,26 @@ module maze_game_top(clk, reset, hsync, vsync, rgb);
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wire [8:0] vpos;
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// video RAM bus
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wire [7:0] vram_read;
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reg [7:0] vram_write = 0;
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reg vram_writeenable = 0;
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wire [15:0] ram_read;
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reg [15:0] ram_write = 0;
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reg ram_writeenable = 0;
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// multiplex sprite and tile RAM
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wire sprite_ram_select = (vpos == 256);
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reg [15:0] tile_ram_addr;
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reg [6:0] sprite_ram_addr;
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reg [5:0] sprite_ram_addr;
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wire tile_reading;
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wire sprite_reading;
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wire [14:0] mux_ram_addr; // 15-bit RAM access
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always @(*)
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if (cpu_busy) begin
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if (sprite_ram_select)
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mux_ram_addr = {9'b1111111, sprite_ram_addr};
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else
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mux_ram_addr = tile_ram_addr[14:0];
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end else
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mux_ram_addr = cpu_ram_addr[14:0];
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// tile and sprite ROM
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wire [10:0] tile_rom_addr;
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@ -48,15 +59,13 @@ module maze_game_top(clk, reset, hsync, vsync, rgb);
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.vpos(vpos)
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);
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// video RAM (16k)
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RAM #(14,8) vram(
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// RAM (32k x 16 bits)
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RAM_sync #(15,16) ram(
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.clk(clk),
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.dout(vram_read),
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.din(vram_write),
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.addr(sprite_ram_select
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? {7'b0111111, sprite_ram_addr}
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: tile_ram_addr[13:0]),
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.we(vram_writeenable)
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.dout(ram_read),
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.din(ram_write),
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.addr(mux_ram_addr),
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.we(ram_writeenable)
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);
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tile_renderer tile_gen(
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@ -66,7 +75,8 @@ module maze_game_top(clk, reset, hsync, vsync, rgb);
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.vpos(vpos),
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.display_on(display_on),
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.ram_addr(tile_ram_addr),
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.ram_read(vram_read),
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.ram_read(ram_read),
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.ram_busy(tile_reading),
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.rom_addr(tile_rom_addr),
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.rom_data(tile_rom_data),
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.rgb(tile_rgb)
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@ -78,7 +88,8 @@ module maze_game_top(clk, reset, hsync, vsync, rgb);
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.hpos(hpos),
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.vpos(vpos),
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.ram_addr(sprite_ram_addr),
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.ram_data(vram_read),
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.ram_data(ram_read),
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.ram_busy(sprite_reading),
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.rom_addr(sprite_rom_addr),
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.rom_data(sprite_rom_data),
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.rgb(sprite_rgb)
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@ -93,34 +104,74 @@ module maze_game_top(clk, reset, hsync, vsync, rgb);
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.addr(sprite_rom_addr),
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.data(sprite_rom_data)
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);
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// sprites overlay tiles
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assign rgb = display_on
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? (sprite_rgb>0 ? sprite_rgb : tile_rgb)
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: 0;
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// CPU RAM (32k x 16 bits)
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RAM #(15,16) mram(
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.clk(clk),
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.dout(cpuram_read),
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.din(cpuram_write),
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.addr(cpuram_addr[14:0]),
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.we(cpuram_writeenable)
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);
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reg [15:0] cpuram_read;
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reg [15:0] cpuram_write;
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reg [15:0] cpuram_addr;
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reg cpuram_writeenable;
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// CPU
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reg cpu_hold = 0;
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wire cpu_busy;
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wire [15:0] cpu_ram_addr;
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wire busy;
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wire [15:0] cpu_bus;
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assign cpu_bus = cpu_ram_addr[15]
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? rom[cpu_ram_addr[9:0]]
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: ram_read;
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CPU16 cpu(
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.clk(clk),
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.reset(reset),
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.hold(0),
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.busy(busy),
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.address(cpuram_addr),
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.data_in(cpuram_read),
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.data_out(cpuram_write),
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.write(cpuram_writeenable));
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.hold(tile_reading | sprite_reading),
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.busy(cpu_busy),
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.address(cpu_ram_addr),
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.data_in(cpu_bus),
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.data_out(ram_write),
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.write(ram_writeenable));
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reg [15:0] rom[0:1023];
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`ifdef EXT_INLINE_ASM
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initial begin
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rom = '{
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__asm
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.arch femto16
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.org 0x8000
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.len 1024
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mov sp,@$6fff
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mov dx,@Init
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jsr dx
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mov ax,#0
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mov dx,@Clear
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jsr dx
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reset
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Init:
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mov ax,@$6000 ; screen buffer
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mov bx,@$7e00 ; page table start
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mov cx,#32 ; 32 rows
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InitLoop:
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mov [bx],ax
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mov [ax],ax
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add ax,#32
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inc bx
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dec cx
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bnz InitLoop
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rts
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Clear:
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mov bx,@$7e00
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mov cx,@1024
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ClearLoop:
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mov [bx],ax
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inc bx
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dec cx
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bnz ClearLoop
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rts
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__endasm
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};
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end
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`endif
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endmodule
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@ -3,7 +3,7 @@
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`include "hvsync_generator.v"
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module RAM(clk, addr, din, dout, we);
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module RAM_sync(clk, addr, din, dout, we);
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parameter A = 10; // # of address bits
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parameter D = 8; // # of data bits
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@ -19,9 +19,31 @@ module RAM(clk, addr, din, dout, we);
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= din; // write memory from din
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dout <= mem[addr]; // read memory to dout
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dout <= mem[addr]; // read memory to dout (sync)
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end
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endmodule
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module RAM_async(clk, addr, din, dout, we);
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parameter A = 10; // # of address bits
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parameter D = 8; // # of data bits
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input clk; // clock
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input [A-1:0] addr; // 10-bit address
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input [D-1:0] din; // 8-bit data input
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output [D-1:0] dout; // 8-bit data output
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input we; // write enable
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reg [D-1:0] mem [0:(1<<A)-1]; // 1024x8 bit memory
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= din; // write memory from din
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end
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assign dout = mem[addr]; // read memory to dout (async)
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endmodule
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`endif
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@ -32,7 +32,7 @@ module example_bitmap_rom(addr, data);
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endmodule
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module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
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ram_addr, ram_data,
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ram_addr, ram_data, ram_busy,
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rom_addr, rom_data);
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parameter NB = 5;
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@ -46,8 +46,10 @@ module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
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input [8:0] vpos;
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output [3:0] rgb;
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output [NB+1:0] ram_addr;
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input [7:0] ram_data;
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output [NB:0] ram_addr;
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input [15:0] ram_data;
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output ram_busy;
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output [15:0] rom_addr;
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input [15:0] rom_data;
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@ -87,25 +89,24 @@ module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
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always @(posedge clk) begin
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ram_busy <= 0;
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// reset every frame, don't draw vpos >= 256
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if (reset || vpos[8]) begin
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// load sprites from RAM on line 260
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// 8 cycles per sprite
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if (vpos == 260 && hpos < N*8) begin
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ram_busy <= 1;
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case (hpos[2:0])
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0: begin
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ram_addr <= {load_index, 2'b00};
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3: begin
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ram_addr <= {load_index, 1'b0};
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end
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2: begin
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sprite_xpos[load_index] <= ram_data;
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ram_addr <= {load_index, 2'b01};
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5: begin
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sprite_xpos[load_index] <= ram_data[7:0];
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sprite_ypos[load_index] <= ram_data[15:8];
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ram_addr <= {load_index, 1'b1};
|
||||
end
|
||||
4: begin
|
||||
sprite_ypos[load_index] <= ram_data;
|
||||
ram_addr <= {load_index, 2'b10};
|
||||
end
|
||||
6: begin
|
||||
sprite_attr[load_index] <= ram_data;
|
||||
7: begin
|
||||
sprite_attr[load_index] <= ram_data[7:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -202,13 +203,14 @@ module test_scanline_render_top(clk, reset, hsync, vsync, rgb);
|
||||
.data(rom_data)
|
||||
);
|
||||
|
||||
wire [6:0] ram_addr;
|
||||
wire [7:0] ram_read;
|
||||
reg [7:0] ram_write;
|
||||
wire [5:0] ram_addr;
|
||||
wire [15:0] ram_read;
|
||||
reg [15:0] ram_write;
|
||||
reg ram_we;
|
||||
wire ram_busy;
|
||||
|
||||
// 128-byte RAM
|
||||
RAM #(7,8) ram(
|
||||
// 64-word RAM
|
||||
RAM_sync #(6,16) ram(
|
||||
.clk(clk),
|
||||
.addr(ram_addr),
|
||||
.dout(ram_read),
|
||||
@ -224,6 +226,7 @@ module test_scanline_render_top(clk, reset, hsync, vsync, rgb);
|
||||
.rgb(rgb),
|
||||
.ram_addr(ram_addr),
|
||||
.ram_data(ram_read),
|
||||
.ram_busy(ram_busy),
|
||||
.rom_addr(rom_addr),
|
||||
.rom_data(rom_data)
|
||||
);
|
||||
@ -231,13 +234,13 @@ module test_scanline_render_top(clk, reset, hsync, vsync, rgb);
|
||||
always @(posedge clk) begin
|
||||
// wiggle sprites randomly once per frame
|
||||
if (vpos == 256) begin
|
||||
ram_addr <= hpos[8:2];
|
||||
ram_addr <= hpos[7:2];
|
||||
// 4 clocks per read/write cycle
|
||||
if (!hpos[1]) begin
|
||||
ram_we <= 0;
|
||||
end else begin
|
||||
ram_we <= 1;
|
||||
ram_write <= ram_read + 8'(($random&3)-1);
|
||||
ram_write <= ram_read + 16'(($random&3)-1);
|
||||
end
|
||||
end else
|
||||
ram_we <= 0;
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
module tile_renderer(clk, reset, hpos, vpos, display_on,
|
||||
rgb,
|
||||
ram_addr, ram_read,
|
||||
ram_addr, ram_read, ram_busy,
|
||||
rom_addr, rom_data);
|
||||
|
||||
input clk, reset;
|
||||
@ -14,12 +14,13 @@ module tile_renderer(clk, reset, hpos, vpos, display_on,
|
||||
output [3:0] rgb;
|
||||
|
||||
output reg [15:0] ram_addr;
|
||||
input [7:0] ram_read;
|
||||
input [15:0] ram_read;
|
||||
output reg ram_busy;
|
||||
|
||||
output [10:0] rom_addr;
|
||||
input [7:0] rom_data;
|
||||
|
||||
reg [7:0] page_base = 0; // page table base (8 bits)
|
||||
reg [7:0] page_base = 8'h7e; // page table base (8 bits)
|
||||
reg [15:0] row_base; // row table base (16 bits)
|
||||
|
||||
wire [4:0] row = vpos[7:3]; // 5-bit row, vpos / 8
|
||||
@ -29,35 +30,39 @@ module tile_renderer(clk, reset, hpos, vpos, display_on,
|
||||
|
||||
reg [7:0] char;
|
||||
reg [7:0] attr;
|
||||
reg [7:0] next_char;
|
||||
reg [7:0] next_attr;
|
||||
|
||||
// tile ROM address
|
||||
assign rom_addr = {char, yofs};
|
||||
|
||||
reg [15:0] row_buffer[0:31];
|
||||
|
||||
// lookup char and attr
|
||||
always @(posedge clk)
|
||||
if (hpos[8]) begin
|
||||
always @(posedge clk) begin
|
||||
// time to read a row?
|
||||
if (vpos[2:0] == 7) begin
|
||||
// read row_base from page table (2 bytes)
|
||||
case (hpos[7:0])
|
||||
// read row_base from page table (2 bytes)
|
||||
// TODO: why 2 cycles?
|
||||
0: ram_addr <= {page_base, row, 3'b000};
|
||||
2: row_base[7:0] <= ram_read;
|
||||
3: ram_addr <= {page_base, row, 3'b001};
|
||||
5: row_base[15:8] <= ram_read;
|
||||
186: ram_busy <= 1;
|
||||
190: ram_addr <= {page_base, 3'b000, row};
|
||||
192: row_base <= ram_read;
|
||||
192+32: ram_busy <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
// load row of tile data from RAM
|
||||
if (hpos >= 192 && hpos < 192+32) begin
|
||||
ram_addr <= row_base + 16'(hpos[4:0]);
|
||||
row_buffer[hpos[4:0]-2] <= ram_read;
|
||||
end
|
||||
end
|
||||
// latch character data
|
||||
if (hpos < 256) begin
|
||||
case (hpos[2:0])
|
||||
0: ram_addr <= row_base + 16'(col);
|
||||
2: next_char <= ram_read;
|
||||
3: ram_addr <= row_base + 16'(col) + 32;
|
||||
5: next_attr <= ram_read;
|
||||
7: begin
|
||||
char <= next_char;
|
||||
attr <= next_attr;
|
||||
char <= row_buffer[col][7:0];
|
||||
attr <= row_buffer[col][15:8];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// extract bit from ROM output
|
||||
assign rgb = display_on
|
||||
@ -77,12 +82,13 @@ module test_tilerender_top(clk, reset, hsync, vsync, rgb);
|
||||
wire [8:0] vpos;
|
||||
|
||||
reg [15:0] ram_addr;
|
||||
wire [7:0] ram_read;
|
||||
reg [7:0] ram_write = 0;
|
||||
wire [15:0] ram_read;
|
||||
reg [15:0] ram_write = 0;
|
||||
reg ram_writeenable = 0;
|
||||
|
||||
wire [10:0] rom_addr;
|
||||
wire [7:0] rom_data;
|
||||
wire ram_busy;
|
||||
|
||||
hvsync_generator hvsync_gen(
|
||||
.clk(clk),
|
||||
@ -95,7 +101,7 @@ module test_tilerender_top(clk, reset, hsync, vsync, rgb);
|
||||
);
|
||||
|
||||
// RAM
|
||||
RAM #(16,8) ram(
|
||||
RAM_sync #(16,16) ram(
|
||||
.clk(clk),
|
||||
.dout(ram_read),
|
||||
.din(ram_write),
|
||||
@ -111,6 +117,7 @@ module test_tilerender_top(clk, reset, hsync, vsync, rgb);
|
||||
.display_on(display_on),
|
||||
.ram_addr(ram_addr),
|
||||
.ram_read(ram_read),
|
||||
.ram_busy(ram_busy),
|
||||
.rom_addr(rom_addr),
|
||||
.rom_data(rom_data),
|
||||
.rgb(rgb)
|
||||
|
||||
@ -23,6 +23,7 @@ var VERILOG_PRESETS = [
|
||||
{id:'framebuffer.v', name:'Frame Buffer'},
|
||||
{id:'tile_renderer.v', name:'Tile Renderer'},
|
||||
{id:'sprite_scanline_renderer.v', name:'Sprite Scanline Renderer'},
|
||||
{id:'cpu16.v', name:'16-Bit CPU'},
|
||||
{id:'maze_game.v', name:'Maze Game'},
|
||||
];
|
||||
|
||||
@ -211,6 +212,7 @@ var VerilogPlatform = function(mainElement, options) {
|
||||
var scopeHeight = videoHeight;
|
||||
var scopeImageData;
|
||||
var sdata; // scope data
|
||||
var module_name;
|
||||
|
||||
var yposlist = [];
|
||||
var lasty = [];
|
||||
@ -471,6 +473,7 @@ var VerilogPlatform = function(mainElement, options) {
|
||||
var name = v.name;
|
||||
ctx.fillStyle = name == inspect_sym ? "yellow" : "white";
|
||||
name = name.replace(/__DOT__/g,'.');
|
||||
name = name.replace(module_name+'.','');
|
||||
ctx.textAlign = 'left';
|
||||
ctx.fillStyle = "white";
|
||||
shadowText(ctx, name, 1, yposlist[i]);
|
||||
@ -578,6 +581,7 @@ var VerilogPlatform = function(mainElement, options) {
|
||||
gen = new mod(base);
|
||||
gen.__proto__ = base;
|
||||
current_output = output;
|
||||
module_name = output.name ? output.name.substr(1) : "top";
|
||||
trace_ports = current_output.ports;
|
||||
trace_signals = current_output.ports.concat(current_output.signals);
|
||||
trace_index = 0;
|
||||
|
||||
@ -1151,9 +1151,13 @@ function compileInlineASM(code, platform, options, errors, asmlines) {
|
||||
if (i>0) s += ",";
|
||||
s += 0|out[i];
|
||||
}
|
||||
asmlines = asmout.asmlines;
|
||||
for (var i=0; i<asmlines.length; i++)
|
||||
asmlines[i].line += firstline;
|
||||
if (asmlines) {
|
||||
var al = asmout.asmlines;
|
||||
for (var i=0; i<al.length; i++) {
|
||||
al[i].line += firstline;
|
||||
asmlines.push(al[i]);
|
||||
}
|
||||
}
|
||||
return s;
|
||||
}
|
||||
});
|
||||
@ -1177,7 +1181,7 @@ function compileVerilator(code, platform, options) {
|
||||
var FS = verilator_mod['FS'];
|
||||
FS.writeFile(topmod+".v", code);
|
||||
writeDependencies(options.dependencies, FS, errors, function(d, code) {
|
||||
return compileInlineASM(code, platform, options, errors, asmlines);
|
||||
return compileInlineASM(code, platform, options, errors, null);
|
||||
});
|
||||
starttime();
|
||||
try {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user