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(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm

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This commit is contained in:
Steven Hugg
2021-06-28 15:36:47 -05:00
parent 7b492622c2
commit 9bb79c318f
81 changed files with 8753 additions and 626 deletions
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test/cli/testverilog.js
+6 -4
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@@ -21,11 +21,12 @@ function loadPlatform(msg) {
platform.loadROM("ROM", msg.output);
platform.loadROM("ROM", msg.output);
platform.loadROM("ROM", msg.output);
verilog.vl_finished = verilog.vl_stopped = false;
for (var i=0; i<100000 && !(verilog.vl_finished||verilog.vl_stopped); i++) {
for (var i=0; i<100000 && !platform.isBlocked(); i++) {
platform.tick();
}
assert.ok(!verilog.vl_stopped);
console.log(i, platform.isBlocked(), platform.isStopped());
//assert.ok(platform.isBlocked());
assert.ok(!platform.isStopped());
var state = platform.saveState();
platform.reset();
platform.loadState(state);
@@ -33,7 +34,7 @@ function loadPlatform(msg) {
} catch (e) {
//platform.printErrorCodeContext(e, msg.output.code);
//console.log(msg.intermediate.listing);
console.log(msg.output.code);
//console.log(msg.output.code);
console.log(e);
throw e;
}
@@ -83,6 +84,7 @@ function compileVerilator(filename, code, callback, nerrors) {
function testVerilator(filename, disables, nerrors) {
it('should translate '+filename, function(done) {
console.log(filename);
var csource = ab2str(fs.readFileSync(filename));
for (var i=0; i<(disables||[]).length; i++)
csource = "/* verilator lint_off " + disables[i] + " */\n" + csource;
test/cli/verilog/t_alw_combdly.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_alw_dly.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_alw_split.v
+29 -72
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -13,29 +14,15 @@ module t (/*AUTOARG*/
reg [15:0] m_din;
// OK
// We expect all these blocks should split;
// blocks that don't split should go in t_alw_nosplit.v
reg [15:0] a_split_1, a_split_2;
always @ (/*AS*/m_din) begin
a_split_1 = m_din;
a_split_2 = m_din;
end
// OK
reg [15:0] b_split_1, b_split_2;
always @ (/*AS*/m_din) begin
b_split_1 = m_din;
b_split_2 = b_split_1;
end
// Not OK
reg [15:0] c_split_1, c_split_2;
always @ (/*AS*/m_din) begin
c_split_1 = m_din;
c_split_2 = c_split_1;
c_split_1 = ~m_din;
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
d_split_1 <= m_din;
@@ -43,44 +30,27 @@ module t (/*AUTOARG*/
d_split_1 <= ~m_din;
end
// Not OK
reg [15:0] h_split_1;
reg [15:0] h_split_2;
always @ (posedge clk) begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
// Not Ok
reg [15:0] l_split_1, l_split_2;
always @ (posedge clk) begin
l_split_2 <= l_split_1;
l_split_1 <= l_split_2 | m_din;
end
// OK
reg [15:0] z_split_1, z_split_2;
always @ (posedge clk) begin
z_split_1 <= 0;
z_split_1 <= ~m_din;
end
always @ (posedge clk) begin
z_split_2 <= 0;
z_split_2 <= z_split_1;
// $write(" cyc = %x m_din = %x\n", cyc, m_din);
if (cyc > 2) begin
if (m_din == 16'h0) begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
else begin
h_split_1 <= m_din;
h_split_2 <= ~m_din;
end
end
else begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
end
// (The checker block is an exception, it won't split.)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
@@ -93,39 +63,26 @@ module t (/*AUTOARG*/
m_din <= 16'he11e;
//$write(" A %x %x\n", a_split_1, a_split_2);
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop;
if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop;
if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop;
if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
if (!(z_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
end // always @ (posedge clk)
endmodule
test/cli/verilog/t_alw_splitord.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_array_compare.v
+6 -1
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@@ -2,6 +2,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Andrew Bardsley.
// SPDX-License-Identifier: CC0-1.0
// bug1071
@@ -35,12 +36,16 @@ module t (/*AUTOARG*/
array_3[2] = 4'b0100;
array_3[3] = 4'b0100;
// Comparisons only compare elements 0
array_1_ne_array_2 = array_1 != array_2; // 0
array_1_eq_array_2 = array_1 == array_2; // 0
array_1_ne_array_3 = array_1 != array_3; // 1
array_1_eq_array_3 = array_1 == array_3; // 1
//Not legal: array_rxor = ^ array_1;
//Not legal: array_rxnor = ^~ array_1;
//Not legal: array_ror = | array_1;
//Not legal: array_rand = & array_1;
`ifdef TEST_VERBOSE
$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
test/cli/verilog/t_case_huge_sub3.v
+4 -3
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@@ -1,11 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_case_huge_sub3 (/*AUTOARG*/
// Outputs
outr,
outr,
// Inputs
clk, index
);
test/cli/verilog/t_clk_2in.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`ifndef VERILATOR
module t;
test/cli/verilog/t_clk_condflop.v
+5 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
@@ -111,6 +112,7 @@ module clockgate (clk, sen, ena, gatedclk);
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
// verilator lint_off LATCH
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
@@ -119,6 +121,7 @@ module clockgate (clk, sen, ena, gatedclk);
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on LATCH
// verilator lint_on COMBDLY
endmodule
test/cli/verilog/t_clk_condflop_nord.v
+5 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
@@ -111,6 +112,7 @@ module clockgate (clk, sen, ena, gatedclk);
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
// verilator lint_off LATCH
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
@@ -119,6 +121,7 @@ module clockgate (clk, sen, ena, gatedclk);
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on LATCH
// verilator lint_on COMBDLY
endmodule
test/cli/verilog/t_clk_dpulse.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_clk_dsp.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_clk_first.v
+7 -7
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@@ -1,19 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
input clk;
input fastclk;
reg reset_l;
int cyc;
// TODO: initial cyc = 0;
initial reset_l = 0;
always @ (posedge clk) begin
if (cyc==0) reset_l <= 1'b1;
@@ -33,8 +33,8 @@ module t_clk (/*AUTOARG*/
clk, fastclk, reset_l
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
input clk;
input fastclk;
input reset_l;
// surefire lint_off STMINI
test/cli/verilog/t_clk_gater.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_clk_gen.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_clk_latch.v
+4 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -52,6 +53,7 @@ module t (/*AUTOARG*/
end
// verilator lint_off COMBDLY
// verilator lint_off LATCH
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
test/cli/verilog/t_clk_latchgate.v
+5 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// --------------------------------------------------------
// Bug Description:
@@ -110,11 +111,13 @@ module llq (clk, d, q);
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
/* verilator lint_off LATCH */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on LATCH */
/* verilator lint_on COMBDLY */
assign q = qr;
test/cli/verilog/t_clk_powerdn.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_clk_vecgen1.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_gen_alw.v
+4 -1
View File
@@ -1,4 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -53,7 +56,7 @@ module t (/*AUTOARG*/
endmodule
module test_top (/*AUTOARG*/
module Test (/*AUTOARG*/
// Inputs
clk, in
);
test/cli/verilog/t_math_arith.v
+133 -88
View File
@@ -1,14 +1,15 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
@@ -28,8 +29,8 @@ module t (/*AUTOARG*/
wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
: (xor2 == 2'b00) ? 5'h2
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
@@ -48,94 +49,138 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
_ranit <= 1;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
ma = 3'h3;
// X propagation
if (!1'bx !== 1'bx) $stop;
if (~2'bx !== 2'bx) $stop;
if (-2'bx !== 2'bx) $stop;
if ((2'bxx + 2'b1) !== 2'bxx) $stop;
if ((2'bxx - 2'b1) !== 2'bxx) $stop;
if ((2'bxx * 2'b1) !== 2'bxx) $stop;
if ((2'bxx / 2'b1) !== 2'bxx) $stop;
if ((2'bxx % 2'b1) !== 2'bxx) $stop;
if ((2'sbxx * 2'sb1) !== 2'bxx) $stop;
if ((2'sbxx / 2'sb1) !== 2'bxx) $stop;
if ((2'sbxx % 2'sb1) !== 2'bxx) $stop;
if ((1'bx & 1'b1) !== 1'bx) $stop;
if ((1'bx & 1'b0) !== 1'b0) $stop;
if ((1'bx | 1'b0) !== 1'bx) $stop;
if ((1'bx | 1'b1) !== 1'b1) $stop;
if ((1'bx && 1'b1) !== 1'bx) $stop;
if ((1'bx && 1'b0) !== 1'b0) $stop;
if ((1'bx || 1'b0) !== 1'bx) $stop;
if ((1'bx || 1'b1) !== 1'b1) $stop;
if ((2'bxx ^ 2'b1) !== 2'bxx) $stop;
if ((2'bxx > 2'b1) !== 1'bx) $stop;
if ((2'bxx < 2'b1) !== 1'bx) $stop;
if ((2'bxx == 2'b1) !== 1'bx) $stop;
if ((2'bxx <= 2'b1) !== 1'bx) $stop;
if ((2'bxx >= 2'b1) !== 1'bx) $stop;
if ((2'sbxx <= 2'sb1) !== 1'bx) $stop;
if ((2'sbxx >= 2'sb1) !== 1'bx) $stop;
ma = 3'h3;
mb = 3'h4;
mc = 10'h5;
mc = 10'h5;
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
// surefire lint_on SEQASS
// surefire lint_on SEQASS
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
$write("*-* All Finished *-*\n");
$finish;
if ((0 -> 0) != 1'b1) $stop;
if ((0 -> 1) != 1'b1) $stop;
if ((1 -> 0) != 1'b0) $stop;
if ((1 -> 1) != 1'b1) $stop;
if ((0 <-> 0) != 1'b1) $stop;
if ((0 <-> 1) != 1'b0) $stop;
if ((1 <-> 0) != 1'b0) $stop;
if ((1 <-> 1) != 1'b1) $stop;
// bug2912
// verilator lint_off WIDTH
if (2'(~1'b1) != 2'b10) $stop;
// verilator lint_on WIDTH
$write("*-* All Finished *-*\n");
$finish;
end
end
@@ -145,13 +190,13 @@ module t (/*AUTOARG*/
reg [7:0] m_corr_data_b8;
initial begin
m_data_pipe2_r = 64'h1234_5678_9abc_def0;
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
if (m_corr_data_w0 != 32'haf36de00) $stop;
if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
if (m_corr_data_b8 != 8'h12) $stop;
test/cli/verilog/t_math_const.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_math_div.v
+21 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -14,12 +15,20 @@ module t (/*AUTOARG*/
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg [60:0] qq4;
reg [60:0] rq4;
reg [60:0] qq5;
reg [60:0] rq5;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qq4 = a[60:0] / 4; // Check power-of-two constification
rq4 = a[60:0] % 4;
qq5 = a[60:0] / 5; // Non power-of-two
rq5 = a[60:0] % 5;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
@@ -34,6 +43,10 @@ module t (/*AUTOARG*/
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc > 1) begin
if (qq4 != {2'b0, a[60:2]}) $stop;
if (rq4 != {59'h0, a[1:0]}) $stop;
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
@@ -42,6 +55,8 @@ module t (/*AUTOARG*/
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
if (qq4 != 61'h01247cf6851f9fc9) $stop;
if (rq4 != 61'h0000000000000002) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
@@ -51,6 +66,8 @@ module t (/*AUTOARG*/
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
if (qq4 != 61'h0292380e727ce56e) $stop;
if (rq4 != 61'h0000000000000000) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
@@ -58,6 +75,8 @@ module t (/*AUTOARG*/
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
if (qq4 != 61'h07482923803ce56e) $stop;
if (rq4 != 61'h0000000000000000) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
test/cli/verilog/t_math_div0.v
+23 -1
View File
@@ -1,10 +1,32 @@
module t(y);
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Outputs
y, d2, m2, d3, m3
);
output [3:0] y;
output [31:0] d2;
output [31:0] m2;
output [63:0] d3;
output [63:0] m3;
// bug775
// verilator lint_off WIDTH
assign y = ((0/0) ? 1 : 2) % 0;
// bug2460
reg [31:0] b;
assign d2 = $signed(32'h80000000) / $signed(b);
assign m2 = $signed(32'h80000000) % $signed(b);
reg [63:0] b3;
assign d3 = $signed(64'h80000000_00000000) / $signed(b3);
assign m3 = $signed(64'h80000000_00000000) % $signed(b3);
initial begin
b = 32'hffffffff;
b3 = 64'hffffffff_ffffffff;
$write("*-* All Finished *-*\n");
$finish;
end
test/cli/verilog/t_math_divw.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_mem.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_order.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_order_2d.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2015 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_order_a.v
+6 -4
View File
@@ -1,11 +1,13 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12,
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11,
o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
@@ -23,7 +25,7 @@ module t_order_a (/*AUTOARG*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
test/cli/verilog/t_order_b.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_order_b (/*AUTOARG*/
// Outputs
test/cli/verilog/t_order_clkinst.v
+40 -37
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -10,14 +11,16 @@ module t (/*AUTOARG*/
input clk;
// verilator lint_off COMBDLY
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off BLKANDNBLK
reg c1_start; initial c1_start = 0;
reg c1_start; initial c1_start = 0;
wire [31:0] c1_count;
comb_loop c1 (.count(c1_count), .start(c1_start));
wire s2_start = (c1_count==0 && c1_start);
wire s2_start = c1_start;
wire [31:0] s2_count;
seq_loop s2 (.count(s2_count), .start(s2_start));
@@ -30,25 +33,29 @@ module t (/*AUTOARG*/
//$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
c1_start <= 1'b0;
end
8'd01: begin
c1_start <= 1'b1;
end
default: ;
8'd00: begin
c1_start <= 1'b0;
end
8'd01: begin
c1_start <= 1'b1;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (c1_count!=32'h3) $stop;
if (s2_count!=32'h3) $stop;
if (c3_count!=32'h6) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
8'd02: begin
// On Verilator, we expect these comparisons to match exactly,
// confirming that our settle loop repeated the exact number of
// iterations we expect. No '$stop' should be called here, and we
// should reach the normal '$finish' below on the next cycle.
if (c1_count!=32'h3) $stop;
if (s2_count!=32'h3) $stop;
if (c3_count!=32'h5) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
@@ -62,12 +69,10 @@ module comb_loop (/*AUTOARG*/
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner = 3;
end
always @ (posedge start) begin
runner = 3;
end
always @ (/*AS*/runner) begin
@@ -76,9 +81,9 @@ module comb_loop (/*AUTOARG*/
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner = runnerm1;
$write ("%m count=%d runner =%x\n",count, runnerm1);
count = count + 1;
runner = runnerm1;
$write ("%m count=%d runner =%x\n",count, runnerm1);
end
end
@@ -93,12 +98,10 @@ module seq_loop (/*AUTOARG*/
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner <= 3;
end
always @ (posedge start) begin
runner <= 3;
end
always @ (/*AS*/runner) begin
@@ -107,9 +110,9 @@ module seq_loop (/*AUTOARG*/
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner <= runnerm1;
$write ("%m count=%d runner<=%x\n",count, runnerm1);
count = count + 1;
runner <= runnerm1;
$write ("%m count=%d runner<=%x\n",count, runnerm1);
end
end
test/cli/verilog/t_order_comboclkloop.v
+4 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -11,6 +12,7 @@ module t (/*AUTOARG*/
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
test/cli/verilog/t_order_comboloop.v
+5 -3
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -10,6 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=1;
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
@@ -38,7 +40,7 @@ module t (/*AUTOARG*/
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but insures our change detection is working properly
// This isn't "regular" beh code, but ensures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
test/cli/verilog/t_order_doubleloop.v
+4 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -10,6 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=1;
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
test/cli/verilog/t_order_first.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_order_loop_bad.v
+4 -3
View File
@@ -8,6 +8,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -15,7 +16,7 @@ module t (/*AUTOARG*/
);
input clk;
reg ready;
reg ready;
initial begin
ready = 1'b0;
@@ -23,8 +24,8 @@ module t (/*AUTOARG*/
always @(posedge ready) begin
if ((ready === 1'b1)) begin
$write("*-* All Finished *-*\n");
$finish;
$write("*-* All Finished *-*\n");
$finish;
end
end
test/cli/verilog/t_order_multialways.v
+3 -2
View File
@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_order_multidriven.v
+4 -3
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@@ -2,11 +2,12 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ted Campbell.
// SPDX-License-Identifier: CC0-1.0
//With MULTI_CLK defined shows bug, without it is hidden
`define MULTI_CLK
//bug634
//bug634
module t (
input i_clk_wr,
@@ -162,13 +163,13 @@ module FooMemImpl(
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output [7:0] a_rdata,
output reg [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output [7:0] b_rdata
output reg [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
test/cli/verilog/t_order_quad.v
+4 -3
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//bug 762
module t(a0, y);
@@ -12,5 +13,5 @@ module t(a0, y);
assign y[30] = 0;
// verilator lint_off UNOPTFLAT
assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 };
endmodule
test/cli/verilog/t_order_wireloop.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
test/cli/verilog/t_tri_gen.v
+5 -4
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -36,8 +37,8 @@ module updown #(parameter UP=0)
endgenerate
endmodule
module t_up (inout tri1 z);
module t_up (inout tri1 z);
endmodule
module t_down (inout tri0 z);
module t_down (inout tri0 z);
endmodule
test/cli/verilog/t_tri_graph.v
+2 -1
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@@ -1,9 +1,10 @@
// DESCRIPTION: Verilator: Unsupported tristate constructur error
// DESCRIPTION: Verilator: Unsupported tristate construct error
//
// This is a compile only regression test of tristate handling for bug514
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_tri_ifbegin.v
+7 -5
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@@ -1,13 +1,16 @@
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module top (/*AUTOARG*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
tri pad_io_h;
tri pad_io_l;
tri pad_io_h;
tri pad_io_l;
sub sub (.*);
@@ -45,8 +48,7 @@ module sub (/*AUTOARG*/
if (DIFFERENTIAL)
assign pad_io_l = sig_l_r;
end
end
end
endgenerate
endmodule
test/cli/verilog/t_tri_inout.v
+4 -1
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@@ -1,5 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
// without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0
module top (input A, input B, input SEL, output Y1, output Y2, output Z);
io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1));
test/cli/verilog/t_tri_inout2.v
+4 -5
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -22,7 +23,6 @@ module t (/*AUTOARG*/
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
initial in=0;
initial en=0;
// Test loop
always @ (posedge clk) begin
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/
end
if (in==3) begin
$write("*-* All Finished *-*\n");
$write("*-* All Finished *-*\n");
$finish;
end
end
@@ -74,4 +74,3 @@ endmodule
module ChildB(input A, output Y);
assign Y = A;
endmodule
test/cli/verilog/t_tri_pullup.v
+4 -1
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@@ -1,5 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
// without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0
module top (input A, input OE, output X, output Y, output Z);
test/cli/verilog/t_tri_select_unsized.v
+2 -1
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@@ -4,6 +4,7 @@
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
@@ -13,7 +14,7 @@ module t (/*AUTOARG*/
wire [1:0] b;
wire [1:0] c;
wire [0:0] d; // Explicit width due to issue 508
wire [0:0] d; // Explicit width due to issue 508
wire [0:0] e;
// This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It
test/cli/verilog/t_tri_unconn.v
+3 -2
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@@ -1,7 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
test/cli/verilog/t_tri_various.v
+4 -2
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@@ -1,5 +1,8 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
// without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
@@ -208,4 +211,3 @@ endmodule
// end
// end
//endmodule
test/cli/workertestutils.js
+5 -2
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@@ -1,18 +1,21 @@
var _require = require;
var assert = require('assert');
var fs = require('fs');
var vm = require('vm');
var worker = {};
process.exit = function() { console.log("arggh you can't exit when i pass noExitRuntime! lol process.exit() go brrr") }
global.window = global;
global.exports = {};
global.self = global;
global.location = {href:'.'};
global.require = (modname) => {
console.log("REQUIRE",modname);
//console.log("REQUIRE",modname);
if (modname == 'path')
return require(modname);
return _require(modname);
};
global.btoa = require('btoa');