diff --git a/doc/notes.txt b/doc/notes.txt
index 5bb0b6ab..a7a055c8 100644
--- a/doc/notes.txt
+++ b/doc/notes.txt
@@ -209,6 +209,7 @@ TODO:
 - show current tool for file
 - download non-text incbin source file
 - show hidden header files that only exist in Emscripten FS
+- WASI modules: https://docs.wasmer.io/integrations/js/wasi/browser
 
 Probing
 - probe log doesn't start @ reset
@@ -414,7 +415,7 @@ Emulator Lib
 - MAME
   - debugging?
   - kbd instructions don't work
-  
+  - https://emscripten.org/docs/porting/asyncify.html
 
 Markdown (showdown) interface
 - add code patches to files
@@ -553,3 +554,4 @@ extern void do_func(void)
 #pragma warnings
 CFG files
 
+
diff --git a/src/platform/c64.ts b/src/platform/c64.ts
index e21ad829..a1b16a4e 100644
--- a/src/platform/c64.ts
+++ b/src/platform/c64.ts
@@ -1,6 +1,6 @@
 
 import { C64_WASMMachine } from "../machine/c64";
-import { Platform, Base6502MachinePlatform, getToolForFilename_6502, getOpcodeMetadata_6502 } from "../common/baseplatform";
+import { Platform, Base6502MachinePlatform, getToolForFilename_6502, getOpcodeMetadata_6502, BaseMAMEPlatform } from "../common/baseplatform";
 import { PLATFORMS } from "../common/emu";
 
 const C64_PRESETS = [
@@ -58,5 +58,38 @@ class C64WASMPlatform extends Base6502MachinePlatform<C64_WASMMachine> implement
   }
 }
 
+// C64 MAME platform
+abstract class C64MAMEPlatform extends BaseMAMEPlatform {
+  getPresets() { return C64_PRESETS; }
+  getToolForFilename = getToolForFilename_6502;
+  getOpcodeMetadata = getOpcodeMetadata_6502;
+  getDefaultExtension() { return ".c"; }
+  loadROM(title, data) {
+    if (!this.started) {
+      this.startModule(this.mainElement, {
+        jsfile:'mame8bitws.js',
+        biosfile:'c64.zip',
+        cfgfile:'c64.cfg',
+        driver:'c64',
+        width:336*2,
+        height:225*2,
+        romfn:'/emulator/disk.d64',
+        romdata:new Uint8Array(data),
+        romsize:0x2000,
+        preInit:function(_self) {
+        },
+      });
+    } else {
+      this.loadROMFile(data);
+      this.loadRegion(":cartleft:cart:rom", data);
+    }
+  }
+  start() {
+  }
+  getMemoryMap() { return C64_MEMORY_MAP; }
+}
+
+
 PLATFORMS['c64'] = C64WASMPlatform;
 PLATFORMS['c64.wasm'] = C64WASMPlatform;
+PLATFORMS['c64.mame'] = C64MAMEPlatform;
diff --git a/src/platform/verilog.ts b/src/platform/verilog.ts
index 0ab8a1dc..e29bc957 100644
--- a/src/platform/verilog.ts
+++ b/src/platform/verilog.ts
@@ -608,11 +608,11 @@ var VerilogPlatform = function(mainElement, options) {
           trace_signals = trace_signals.filter((v) => { return IGNORE_SIGNALS.indexOf(v.name)<0; }); // remove clk, reset
           $("#speed_bar").show();
           $("#run_bar").show();
-          $("#xtra_bar").show();
+          $("#dbg_record").show();
         } else {
           $("#speed_bar").hide();
           $("#run_bar").hide();
-          $("#xtra_bar").hide();
+          $("#dbg_record").hide();
         }
       }
     }
diff --git a/src/worker/workermain.ts b/src/worker/workermain.ts
index f0cb14f6..f0f8ef0d 100644
--- a/src/worker/workermain.ts
+++ b/src/worker/workermain.ts
@@ -1776,7 +1776,6 @@ function compileVerilator(step:BuildStep) {
   var errors : WorkerError[] = [];
   gatherFiles(step);
   // compile verilog if files are stale
-  var xmlPath = "main.xml";
   if (staleFiles(step, [xmlPath])) {
     // TODO: %Error: Specified --top-module 'ALU' isn't at the top level, it's under another cell 'cpu'
     // TODO: ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
@@ -1809,12 +1808,13 @@ function compileVerilator(step:BuildStep) {
       }
     });
     starttime();
+    var xmlPath = `obj_dir/V${topmod}.xml`;
     try {
       var args = ["--cc", "-O3"/*abcdefstzsuka*/, "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod,
         "-Wall",
         "-Wno-DECLFILENAME", "-Wno-UNUSED", "-Wno-EOFNEWLINE", "-Wno-PROCASSWIRE",
         "--x-assign", "fast", "--noassert", "--pins-sc-biguint",
-        "--xml-output", xmlPath,
+        "--debug-check", // for XML output
         "--top-module", topmod, step.path]
       verilator_mod.callMain(args);
     } catch (e) {