verilog: disabled v4 warnings, inline asm in non-main files
This commit is contained in:
Steven Hugg
parent
d0838ec954
commit
aa7fe61a86
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@ -1,4 +1,4 @@
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--- index.html 2021-07-09 15:15:12.000000000 -0500
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--- index.html 2021-07-11 18:38:37.000000000 -0500
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+++ electron.html 2021-07-10 13:34:48.000000000 -0500
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@@ -3,18 +3,7 @@
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@ -69,7 +69,7 @@
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</ul>
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</li>
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<li class="dropdown dropdown-submenu">
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@@ -110,36 +63,6 @@
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@@ -110,35 +63,6 @@
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<li><a class="dropdown-item" href="#" id="item_debug_expr">Break Expression...</a></li>
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</ul>
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</li>
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@ -92,12 +92,11 @@
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- <li class="dropdown dropdown-submenu">
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- <a tabindex="-1" href="#">About</a>
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- <ul class="dropdown-menu">
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- <li><a class="dropdown-item" target="_8bws_about" href="https://8bitworkshop.com/blog">Latest News</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://8bitworkshop.com/projects">Projects</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://8bitworkshop.com/">Website</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://twitter.com/8bitworkshop">Twitter</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://github.com/sehugg/8bitworkshop">GitHub</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://8bitworkshop.com/docs/blog.html">Latest News</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://github.com/sehugg/8bitworkshop/issues/new">Report an Issue</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://8bitworkshop.com/blog/docs/ide.md.html">IDE Help</a></li>
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- <li><a class="dropdown-item" target="_8bws_about" href="https://8bitworkshop.com/docs/docs/ide.html">User Manual</a></li>
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- </ul>
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- </li>
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- <!--
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@ -106,7 +105,7 @@
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</ul>
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</span>
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@@ -235,41 +158,8 @@
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@@ -234,41 +158,8 @@
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<span class="label"><span id="settle_label"></span> evals/clk</span>
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</span>
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@ -149,7 +148,7 @@
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</div><!-- controls_dynamic -->
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</div><!-- controls_top -->
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@@ -453,73 +343,6 @@
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@@ -452,73 +343,6 @@
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</div>
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</div>
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</div>
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@ -223,7 +222,7 @@
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<script src="jquery/jquery.min.js"></script>
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@@ -614,28 +437,5 @@
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@@ -613,28 +437,5 @@
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startUI();
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</script>
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@ -54,7 +54,7 @@
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"vgm-parser": "^0.6.3"
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},
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"scripts": {
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"build": "make",
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"build": "tsc --build tsconfig.json",
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"test": "npm run test-node",
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"test-one": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000",
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"test-node": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 --reporter mocha-simple-html-reporter --reporter-options output=test/output/cli.html test/cli",
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@ -0,0 +1,54 @@
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{
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"name":"riscv",
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"vars":{
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"reg":{"bits":5, "toks":["zero","x1","x2","x3","x4","x5","x6","x7","x8","x9","x10","x11","x12","x13","x14","x15"]},
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"brop":{"bits":3, "toks":["beq","bne","bx2","bx3","blt","bge","bltu","bgeu"]},
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"imm5":{"bits":5},
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"imm12":{"bits":12},
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"imm20":{"bits":20},
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"rel13":{"bits":13, "iprel":true, "ipofs":0, "ipmul":4},
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"rel20":{"bits":20, "iprel":true, "ipofs":0, "ipmul":4}
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},
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"rules":[
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{"fmt":"add ~reg,~reg,~reg", "bits":["0000000",2,1,"000",0,"0110011"]},
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{"fmt":"sub ~reg,~reg,~reg", "bits":["0100000",2,1,"000",0,"0110011"]},
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{"fmt":"xor ~reg,~reg,~reg", "bits":["0000000",2,1,"100",0,"0110011"]},
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{"fmt":"or ~reg,~reg,~reg", "bits":["0000000",2,1,"110",0,"0110011"]},
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{"fmt":"and ~reg,~reg,~reg", "bits":["0000000",2,1,"111",0,"0110011"]},
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{"fmt":"sll ~reg,~reg,~reg", "bits":["0000000",2,1,"001",0,"0110011"]},
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{"fmt":"srl ~reg,~reg,~reg", "bits":["0000000",2,1,"101",0,"0110011"]},
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{"fmt":"sra ~reg,~reg,~reg", "bits":["0100000",2,1,"101",0,"0110011"]},
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{"fmt":"slt ~reg,~reg,~reg", "bits":["0000000",2,1,"010",0,"0110011"]},
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{"fmt":"sltu ~reg,~reg,~reg", "bits":["0000000",2,1,"011",0,"0110011"]},
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{"fmt":"addi ~reg,~reg,~imm12", "bits":[2,1,"000",0,"0010011"]},
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{"fmt":"xori ~reg,~reg,~imm12", "bits":[2,1,"100",0,"0010011"]},
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{"fmt":"ori ~reg,~reg,~imm12", "bits":[2,1,"110",0,"0010011"]},
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{"fmt":"andi ~reg,~reg,~imm12", "bits":[2,1,"111",0,"0010011"]},
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{"fmt":"slli ~reg,~reg,~imm5", "bits":["0000000",2,1,"000",0,"0010011"]},
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{"fmt":"srli ~reg,~reg,~imm5", "bits":["0000000",2,1,"000",0,"0010011"]},
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{"fmt":"srai ~reg,~reg,~imm5", "bits":["0100000",2,1,"000",0,"0010011"]},
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{"fmt":"slti ~reg,~reg,~imm12", "bits":[2,1,"010",0,"0010011"]},
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{"fmt":"sltiu ~reg,~reg,~imm12","bits":[2,1,"011",0,"0010011"]},
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{"fmt":"lb ~reg,~imm12(~reg)", "bits":[1,2,"000",0,"0000011"]},
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{"fmt":"lh ~reg,~imm12(~reg)", "bits":[1,2,"001",0,"0000011"]},
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{"fmt":"lw ~reg,~imm12(~reg)", "bits":[1,2,"010",0,"0000011"]},
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{"fmt":"lbu ~reg,~imm12(~reg)", "bits":[1,2,"100",0,"0000011"]},
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{"fmt":"lhu ~reg,~imm12(~reg)", "bits":[1,2,"101",0,"0000011"]},
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{"fmt":"sb ~reg,~imm12(~reg)", "bits":[{"a":1,"b":5,"n":7},2,0,"000",{"a":1,"b":0,"n":5},"0100011"]},
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{"fmt":"sh ~reg,~imm12(~reg)", "bits":[{"a":1,"b":5,"n":7},2,0,"001",{"a":1,"b":0,"n":5},"0100011"]},
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{"fmt":"sw ~reg,~imm12(~reg)", "bits":[{"a":1,"b":5,"n":7},2,0,"010",{"a":1,"b":0,"n":5},"0100011"]},
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{"fmt":"~brop ~reg,~reg,~rel13", "bits":[{"a":3,"b":12,"n":1},{"a":3,"b":5,"n":6},2,1,0,{"a":3,"b":1,"n":4},{"a":3,"b":11,"n":1},"1100011"]},
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{"fmt":"jal ~reg,~rel20", "bits":[{"a":1,"b":20,"n":1},{"a":1,"b":1,"n":10},{"a":1,"b":11,"n":1},{"a":1,"b":12,"n":8},0,"1101111"]},
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{"fmt":"jalr ~reg,~reg,~imm12", "bits":[2,1,"000",0,"1100111"]},
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{"fmt":"lui ~reg,~imm20", "bits":[1,0,"0110111"]},
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{"fmt":"auipc ~reg,~rel20", "bits":[1,0,"0010111"]},
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{"fmt":"brk", "bits":["0000 0000 0000 0000 0000 0000 0000 0000"]}
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]
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}
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@ -366,7 +366,7 @@ type FileEntry = {
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type BuildOptions = {
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mainFilePath : string,
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processFn?: (FileData) => FileData
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processFn?: (s:string, d:FileData) => FileData
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};
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// TODO
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@ -421,8 +421,9 @@ function getWorkFileAsString(path:string) : string {
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function populateEntry(fs, path:string, entry:FileEntry, options:BuildOptions) {
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var data = entry.data;
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if (options && options.processFn)
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data = options.processFn(data);
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if (options && options.processFn) {
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data = options.processFn(path, data);
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}
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// create subfolders
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var toks = path.split('/');
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if (toks.length > 1) {
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@ -1773,7 +1774,6 @@ function compileVerilator(step:BuildStep) {
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loadRequire("vxmlparser", "common/hdl/vxmlparser");
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var platform = step.platform || 'verilog';
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var errors : WorkerError[] = [];
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var asmlines : SourceLine[] = [];
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gatherFiles(step);
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// compile verilog if files are stale
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var xmlPath = "main.xml";
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@ -1793,17 +1793,26 @@ function compileVerilator(step:BuildStep) {
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var code = getWorkFileAsString(step.path);
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var topmod = detectTopModuleName(code);
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var FS = verilator_mod['FS'];
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var listings : CodeListingMap = {};
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// process inline assembly, add listings where found
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populateFiles(step, FS, {
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mainFilePath:step.path,
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processFn:(code) => {
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code = compileInlineASM(code, platform, step, errors, asmlines);
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processFn:(path,code) => {
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if (typeof code === 'string') {
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let asmlines = [];
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code = compileInlineASM(code, platform, step, errors, asmlines);
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if (asmlines.length) {
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listings[path] = {lines:asmlines};
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}
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}
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return code;
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}
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});
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starttime();
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try {
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var args = ["--cc", "-O3"/*abcdefstzsuka*/, "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod,
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"-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat',
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"-Wall",
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"-Wno-DECLFILENAME", "-Wno-UNUSED", "-Wno-EOFNEWLINE", "-Wno-PROCASSWIRE",
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"--x-assign", "fast", "--noassert", "--pins-sc-biguint",
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"--xml-output", xmlPath,
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"--top-module", topmod, step.path]
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@ -1821,11 +1830,11 @@ function compileVerilator(step:BuildStep) {
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}
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starttime();
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var xmlParser = new emglobal['VerilogXMLParser']();
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var listings : CodeListingMap = {};
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try {
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var xmlContent = FS.readFile(xmlPath, {encoding:'utf8'});
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var xmlScrubbed = xmlContent.replace(/ fl=".+?" loc=".+?"/g, '');
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listings[step.prefix + '.lst'] = {lines:[],text:xmlContent};
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// TODO: this squelches the .asm listing
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//listings[step.prefix + '.xml'] = {lines:[],text:xmlContent};
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putWorkFile(xmlPath, xmlScrubbed); // don't detect changes in source position
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if (!anyTargetChanged(step, [xmlPath]))
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return;
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@ -1842,10 +1851,6 @@ function compileVerilator(step:BuildStep) {
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} finally {
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endtime("parse");
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}
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//rtn.intermediate = {listing:h_file + cpp_file}; // TODO
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// TODO: what if found in non-top-module?
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if (asmlines.length)
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listings[step.path] = {lines:asmlines};
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return {
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output: xmlParser,
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errors: errors,
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@ -1,4 +1,5 @@
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// not really femto8
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var EXAMPLE_SPEC = {
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name:'femto8',
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vars:{
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@ -30,6 +31,95 @@ var EXAMPLE_SPEC = {
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]
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}
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var BEAKER8_SPEC = {
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"name": "Beaker8",
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"width": 8,
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"vars": {
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"cb": { "bits": 3, "toks": ["0", "1", "2", "4", "8", "10", "♦", "255"]},
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"cv": { "bits": 3, "toks": ["0", "1", "2", "3", "4", "5", "6", "♦"]},
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"cond": { "bits": 3, "toks": ["♦", "♦", ".z", ".nz", ".c", ".nc", ".s", ".ns"] },
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"ic": { "bits": 3 },
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"abs8": { "bits": 8 },
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"abs16": { "bits": 16 },
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"rel8": { "bits": 8, "iprel": true, "ipofs": 2 }
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},
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"rules": [
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{ "fmt": "const.~cb", "bits": ["00000", 0] },
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{ "fmt": "const.b.~cb", "bits": ["00000", 0] },
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{ "fmt": "const ~abs8", "bits": ["00000110", 0] },
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{ "fmt": "const.b ~abs8", "bits": ["00000110", 0] },
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{ "fmt": "const.b ~abs8", "bits": ["00000110", 0] },
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{ "fmt": "const.w.~cb", "bits": ["00001", 0] },
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{ "fmt": "const.w ~abs16", "bits": ["00001110", 0] },
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{ "fmt": "peek.~cv", "bits": ["00010", 0] },
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{ "fmt": "peek.b.~cv", "bits": ["00010", 0] },
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{ "fmt": "peek ~abs8", "bits": ["00010111", 0] },
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{ "fmt": "peek.b ~abs8", "bits": ["00010111", 0] },
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{ "fmt": "peek.w.~cv", "bits": ["00011", 0] },
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{ "fmt": "peek.w ~abs8", "bits": ["00011111", 0] },
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{ "fmt": "drop.~cv", "bits": ["00101", 0] },
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{ "fmt": "drop ~abs8", "bits": ["00101111", 0] },
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{ "fmt": "send", "bits": ["00101000"] },
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{ "fmt": "send.b", "bits": ["00101000"] },
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{ "fmt": "send ~abs8", "bits": ["00101001", 0] },
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{ "fmt": "send.b ~abs8", "bits": ["00101001", 0] },
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{ "fmt": "send.~cb ~abs8", "bits": ["00000", 0, "00101001", 0] },
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{ "fmt": "send.b.~cb ~abs8", "bits": ["00000", 0, "00101001", 0] },
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{ "fmt": "send ~abs8, ~abs8", "bits": ["00000110", 0, "00101001", 0] },
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{ "fmt": "send.b ~abs8, ~abs8", "bits": ["00000110", 0, "00101001", 0] },
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{ "fmt": "receive", "bits": ["00101010"] },
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{ "fmt": "receive.b", "bits": ["00101010"] },
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{ "fmt": "receive.b ~abs8", "bits": ["00101011", 0] },
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{ "fmt": "copy", "bits": ["00101100"] },
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{ "fmt": "copy.b", "bits": ["00101100"] },
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{ "fmt": "copy.inc", "bits": ["00101110"] },
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{ "fmt": "copy.b.inc", "bits": ["00101110"] },
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{ "fmt": "copy.dec", "bits": ["00101111"] },
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{ "fmt": "copy.b.dec", "bits": ["00101111"] },
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{ "fmt": "read", "bits": ["00110000"] },
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{ "fmt": "read.b", "bits": ["00110000"] },
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{ "fmt": "read ~abs16", "bits": ["00110001", 0] },
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{ "fmt": "read.b ~abs16", "bits": ["00110001", 0] },
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{ "fmt": "read.inc", "bits": ["00110010"] },
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{ "fmt": "read.b.inc", "bits": ["00110010"] },
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{ "fmt": "read.dec", "bits": ["00110011"] },
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{ "fmt": "read.b.dec", "bits": ["00110011"] },
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{ "fmt": "write", "bits": ["00110100"] },
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{ "fmt": "write.b", "bits": ["00110100"] },
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{ "fmt": "write ~abs16", "bits": ["00110101", 0] },
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{ "fmt": "write.b ~abs16", "bits": ["00110101", 0] },
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{ "fmt": "write.inc", "bits": ["00110110"] },
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{ "fmt": "write.b.inc", "bits": ["00110110"] },
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{ "fmt": "write.dec", "bits": ["00110111"] },
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{ "fmt": "write.b.dec", "bits": ["00110111"] },
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{ "fmt": "read.w", "bits": ["00111000"] },
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{ "fmt": "read.w ~abs16", "bits": ["00111001", 0] },
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{ "fmt": "read.w.inc", "bits": ["00111010"] },
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{ "fmt": "read.w.dec", "bits": ["00111011"] },
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{ "fmt": "write.w", "bits": ["00111100"] },
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{ "fmt": "write.w ~abs16", "bits": ["00111101", 0] },
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{ "fmt": "write.w.inc", "bits": ["00111110"] },
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{ "fmt": "write.w.dec", "bits": ["00111111"] },
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{ "fmt": "nop", "bits": ["11100000"] },
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{ "fmt": "halt", "bits": ["11100001"] },
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{ "fmt": "break", "bits": ["11100010"] },
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{ "fmt": "di", "bits": ["11100100"] },
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{ "fmt": "ei", "bits": ["11100101"] },
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{ "fmt": "jump", "bits": ["11101000"] },
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{ "fmt": "jump ~abs16", "bits": ["11101001", 0] },
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{ "fmt": "call", "bits": ["11101010"] },
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{ "fmt": "call ~abs16", "bits": ["11101011", 0] },
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{ "fmt": "read.pc", "bits": ["11101100"] },
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{ "fmt": "djr.nz ~abs8", "bits": ["11101110"] },
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{ "fmt": "djr.b.nz ~abs8", "bits": ["11101110"] },
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{ "fmt": "djr.w.nz ~abs8", "bits": ["11101111"] },
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{ "fmt": "jr", "bits": ["11110000"] },
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{ "fmt": "jr~cond", "bits": ["11110", 0] },
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{ "fmt": "ret", "bits": ["11111000"] },
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{ "fmt": "ret~cond", "bits": ["11111", 0] }
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]
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};
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var vm = require('vm');
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var fs = require('fs');
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var assert = require('assert');
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@ -38,11 +128,16 @@ var includeInThisContext = function(path) {
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vm.runInThisContext(code, path);
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};
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var femto8_spec = JSON.parse(fs.readFileSync('presets/verilog/femto8.json'));
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var femto16_spec = JSON.parse(fs.readFileSync('presets/verilog/femto16.json'));
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var riscv_spec = JSON.parse(fs.readFileSync('presets/verilog/riscv.json'));
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var assembler = require("gen/worker/assembler.js");
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describe('Assemble', function() {
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it('Should assemble', function() {
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var source = `.arch femto8
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it('Should assemble femto8', function() {
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let source = `.arch femto8
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.org 128
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.len 128
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@ -76,8 +171,8 @@ WaitVsync:
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sta 0
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jmp DisplayLoop
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`;
|
||||
var asm = new assembler.Assembler(EXAMPLE_SPEC);
|
||||
var result = asm.assembleFile(source);
|
||||
let asm = new assembler.Assembler(EXAMPLE_SPEC);
|
||||
let result = asm.assembleFile(source);
|
||||
//console.log(result);
|
||||
//assert.equal(result, {});
|
||||
assert.equal(128, result.origin);
|
||||
|
|
@ -115,27 +210,146 @@ WaitVsync:
|
|||
});
|
||||
|
||||
it('Should fail', function() {
|
||||
var source = `.arch femto8
|
||||
let source = `.arch femto8
|
||||
zero C
|
||||
`;
|
||||
var asm = new assembler.Assembler(EXAMPLE_SPEC);
|
||||
var result = asm.assembleFile(source);
|
||||
let asm = new assembler.Assembler(EXAMPLE_SPEC);
|
||||
let result = asm.assembleFile(source);
|
||||
console.log(result);
|
||||
assert.deepEqual(
|
||||
[ { msg: "Can't use 'c' here, only one of: a, b, ip, none", line: 2 } ],
|
||||
result.errors);
|
||||
});
|
||||
/*
|
||||
it('Should fail 2', function() {
|
||||
var source = `.arch femto8
|
||||
mov A, [b]
|
||||
|
||||
it('Should assemble femto16', function() {
|
||||
let source = `
|
||||
.arch femto16
|
||||
.org 0x8000
|
||||
.len 256
|
||||
mov sp,@$6fff
|
||||
mov dx,@Fib
|
||||
jsr dx
|
||||
reset
|
||||
Fib:
|
||||
mov ax,#1
|
||||
mov bx,#0
|
||||
Loop:
|
||||
mov cx,ax
|
||||
add ax,bx
|
||||
mov bx,cx
|
||||
push ax
|
||||
pop ax
|
||||
mov [42],ax
|
||||
mov ax,[42]
|
||||
bcc Loop
|
||||
rts
|
||||
`;
|
||||
var asm = new assembler.Assembler(EXAMPLE_SPEC);
|
||||
var result = asm.assembleFile(source);
|
||||
console.log(result);
|
||||
assert.deepEqual(
|
||||
[ { msg: "Can't use 'c' here, only one of: a, b, ip, none", line: 2 } ],
|
||||
result.errors);
|
||||
let asm = new assembler.Assembler(femto16_spec);
|
||||
let result = asm.assembleFile(source);
|
||||
assert.deepEqual(result.lines, [
|
||||
{ line: 5, offset: 32768, nbits: 32, insns: '1E58 6FFF' },
|
||||
{ line: 6, offset: 32770, nbits: 32, insns: '1B58 8006' },
|
||||
{ line: 7, offset: 32772, nbits: 16, insns: '771E' },
|
||||
{ line: 8, offset: 32773, nbits: 16, insns: 'B8FF' },
|
||||
{ line: 10, offset: 32774, nbits: 16, insns: 'D801' },
|
||||
{ line: 11, offset: 32775, nbits: 16, insns: 'D900' },
|
||||
{ line: 13, offset: 32776, nbits: 16, insns: '0258' },
|
||||
{ line: 14, offset: 32777, nbits: 16, insns: '0061' },
|
||||
{ line: 15, offset: 32778, nbits: 16, insns: '015A' },
|
||||
{ line: 16, offset: 32779, nbits: 16, insns: '5006' },
|
||||
{ line: 17, offset: 32780, nbits: 16, insns: '480E' },
|
||||
{ line: 18, offset: 32781, nbits: 16, insns: '302A' },
|
||||
{ line: 19, offset: 32782, nbits: 16, insns: '282A' },
|
||||
{ line: 20, offset: 32783, nbits: 16, insns: '81F8' },
|
||||
{ line: 21, offset: 32784, nbits: 16, insns: '4F0E' }
|
||||
]);
|
||||
});
|
||||
*/
|
||||
|
||||
it('Should assemble riscv', function() {
|
||||
let source = `
|
||||
.arch riscv
|
||||
.org 0
|
||||
.len 2048
|
||||
.width 32
|
||||
FOO:
|
||||
add x1,x2,x2
|
||||
sub x3,zero,x2
|
||||
xor x4,x3,x2
|
||||
addi x5,x4,1234
|
||||
beq x10,x11,FOO3
|
||||
; .data 0x7cb504e3
|
||||
FOO3:
|
||||
beq x10,x11,FOO ;7CB504E3
|
||||
FOO2:
|
||||
lw x6,12(x6)
|
||||
sb x7,64(x6)
|
||||
sh x7,68(x7)
|
||||
sw x7,72(x7)
|
||||
lui x12,12
|
||||
`;
|
||||
let asm = new assembler.Assembler(riscv_spec);
|
||||
let result = asm.assembleFile(source);
|
||||
assert.deepEqual(result.lines, [
|
||||
{ line: 7, offset: 0, nbits: 32, insns: '002100B3' },
|
||||
{ line: 8, offset: 1, nbits: 32, insns: '402001B3' },
|
||||
{ line: 9, offset: 2, nbits: 32, insns: '0021C233' },
|
||||
{ line: 10, offset: 3, nbits: 32, insns: '4D220293' },
|
||||
{ line: 11, offset: 4, nbits: 32, insns: '00B50263' },
|
||||
{ line: 14, offset: 5, nbits: 32, insns: 'FEB506E3' },
|
||||
{ line: 16, offset: 6, nbits: 32, insns: '00C32303' },
|
||||
{ line: 17, offset: 7, nbits: 32, insns: '04638023' },
|
||||
{ line: 18, offset: 8, nbits: 32, insns: '04739223' },
|
||||
{ line: 19, offset: 9, nbits: 32, insns: '0473A423' },
|
||||
{ line: 20, offset: 10, nbits: 32, insns: '0000C637' }
|
||||
]);
|
||||
});
|
||||
|
||||
it('Should assemble 16-bit constants', function() {
|
||||
let source = `
|
||||
.arch Beaker8
|
||||
.org 0
|
||||
.len 0x4000
|
||||
|
||||
.define vramWrite $00
|
||||
.define vramRead $01
|
||||
|
||||
.define vdpReg0 $40
|
||||
.define vdpReg1 $41
|
||||
.define vdpReg2 $42
|
||||
|
||||
|
||||
boot: di
|
||||
jump Init
|
||||
|
||||
init: call setTextMode
|
||||
halt
|
||||
|
||||
setTextMode:
|
||||
; // set vdp0 border 1, mode 4 (Text)
|
||||
send vdpReg0, $14
|
||||
const.w $2000 ;// length
|
||||
const.w.0 ;// address
|
||||
call clrVram
|
||||
ret
|
||||
|
||||
; // w length
|
||||
; // w address
|
||||
clrVram:
|
||||
; // send address to vdp
|
||||
send vdpReg1
|
||||
send vdpReg2
|
||||
|
||||
; // send 0 to vram
|
||||
_loop:
|
||||
const.0
|
||||
send vramWrite
|
||||
djr.w.nz _loop
|
||||
ret
|
||||
`;
|
||||
let asm = new assembler.Assembler(BEAKER8_SPEC);
|
||||
let result = asm.assembleFile(source);
|
||||
assert.deepEqual(result.lines, [
|
||||
]);
|
||||
})
|
||||
|
||||
});
|
||||
|
|
|
|||
Loading…
Reference in New Issue