From aad8efcfec79be7b408363534f9e0d0f00298b28 Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Wed, 22 Nov 2017 16:31:30 -0500 Subject: [PATCH] added more verilog test cases --- src/worker/verilator2js.js | 31 +-- test/cli/testverilog.js | 21 +- test/cli/verilog/t_case_huge_sub3.v | 291 ++++++++++++++++++++++++ test/cli/verilog/t_gen_alw.v | 87 +++++++ test/cli/verilog/t_order.v | 107 +++++++++ test/cli/verilog/t_order_2d.v | 79 +++++++ test/cli/verilog/t_order_a.v | 52 +++++ test/cli/verilog/t_order_b.v | 18 ++ test/cli/verilog/t_order_clkinst.v | 116 ++++++++++ test/cli/verilog/t_order_comboclkloop.v | 68 ++++++ test/cli/verilog/t_order_comboloop.v | 55 +++++ test/cli/verilog/t_order_doubleloop.v | 99 ++++++++ test/cli/verilog/t_order_first.v | 62 +++++ test/cli/verilog/t_order_loop_bad.v | 41 ++++ test/cli/verilog/t_order_multialways.v | 61 +++++ test/cli/verilog/t_order_multidriven.v | 192 ++++++++++++++++ test/cli/verilog/t_order_quad.v | 16 ++ test/cli/verilog/t_order_wireloop.v | 18 ++ 18 files changed, 1386 insertions(+), 28 deletions(-) create mode 100644 test/cli/verilog/t_case_huge_sub3.v create mode 100644 test/cli/verilog/t_gen_alw.v create mode 100644 test/cli/verilog/t_order.v create mode 100644 test/cli/verilog/t_order_2d.v create mode 100644 test/cli/verilog/t_order_a.v create mode 100644 test/cli/verilog/t_order_b.v create mode 100644 test/cli/verilog/t_order_clkinst.v create mode 100644 test/cli/verilog/t_order_comboclkloop.v create mode 100644 test/cli/verilog/t_order_comboloop.v create mode 100644 test/cli/verilog/t_order_doubleloop.v create mode 100644 test/cli/verilog/t_order_first.v create mode 100644 test/cli/verilog/t_order_loop_bad.v create mode 100644 test/cli/verilog/t_order_multialways.v create mode 100644 test/cli/verilog/t_order_multidriven.v create mode 100644 test/cli/verilog/t_order_quad.v create mode 100644 test/cli/verilog/t_order_wireloop.v diff --git a/src/worker/verilator2js.js b/src/worker/verilator2js.js index e0eb6277..9e1c5a4c 100644 --- a/src/worker/verilator2js.js +++ b/src/worker/verilator2js.js @@ -66,8 +66,9 @@ function translateFunction(text) { var funcname = text.match(/(\w+)/)[1]; text = text.replace(symsName + "* __restrict ", ""); text = text.replace(moduleName + "* __restrict vlTOPp VL_ATTR_UNUSED", "var vlTOPp"); - text = text.replace(/VL_DEBUG_IF/g,"//VL_DEBUG_IF"); - text = text.replace(/VL_SIG(\d*)[(](\w+),(\d+),(\d+)[)]/g, 'var $2'); + text = text.replace(/\bVL_DEBUG_IF\(([^]+?)\);\n/g,"/*VL_DEBUG_IF($1);*/\n"); + //text = text.replace(/\bVL_DEBUG_IF/g,"!__debug__?0:\n"); + text = text.replace(/\bVL_SIG(\d*)[(](\w+),(\d+),(\d+)[)]/g, 'var $2'); text = text.replace(/\b->\b/g, "."); text = text.replace('VL_INLINE_OPT', ''); text = text.replace(/[(]IData[)]/g, ''); @@ -83,6 +84,7 @@ function translateFunction(text) { text = text.replace(/VL_LIKELY/g, '!!'); text = text.replace(/VL_UNLIKELY/g, '!!'); text = text.replace(/Verilated::(\w+)Error/g, 'console.log'); + text = text.replace(/vlSymsp.name[(][)]/g, '"'+moduleName+'"'); return "function " + text + "\nself." + funcname + " = " + funcname + ";\n"; } @@ -131,28 +133,3 @@ function translateVerilatorOutputToJS(htext, cpptext) { } }; } - -//// - -// TODO: unit test -/* -incpp = "obj_dir/Vhvsync_generator.cpp" -inh = "obj_dir/Vhvsync_generator.h" - -fs = require('fs') -fs.readFile(incpp, 'utf8', function (err,datacpp) { - fs.readFile(inh, 'utf8', function (err,datah) { - var modtext = translateVerilatorOutputToJS(datah, datacpp); - console.log(modtext); - var mod = new Function('base',modtext); - var gen = new mod(new VerilatorBase()); - console.log(gen); - gen._ctor_var_reset(); - var top = {TOPp:gen}; - gen._eval_settle(top); - for (var i=0; i<1000000; i++) - gen._eval(top); - console.log(gen); - }); -}); -*/ diff --git a/test/cli/testverilog.js b/test/cli/testverilog.js index 16c23c1f..c86182a4 100644 --- a/test/cli/testverilog.js +++ b/test/cli/testverilog.js @@ -11,8 +11,9 @@ function loadPlatform(msg) { try { platform.loadROM("ROM", msg.output); vl_finished = vl_stopped = false; - for (var i=0; i<100 && !(vl_finished||vl_stopped); i++) + for (var i=0; i<10000 && !(vl_finished||vl_stopped); i++) platform.tick(); + //assert.ok(vl_finished||vl_stopped); } catch (e) { //platform.printErrorCodeContext(e, msg.output.code); console.log(msg.intermediate.listing); @@ -49,6 +50,24 @@ function testVerilator(filename, disables, nerrors) { } describe('Verilog Worker', function() { + testVerilator('test/cli/verilog/t_gen_alw.v'); + testVerilator('test/cli/verilog/t_case_huge_sub3.v'); + + //testVerilator('test/cli/verilog/t_order.v'); + //testVerilator('test/cli/verilog/t_order_2d.v'); + //testVerilator('test/cli/verilog/t_order_a.v'); + //testVerilator('test/cli/verilog/t_order_b.v'); + //testVerilator('test/cli/verilog/t_order_clkinst.v'); + testVerilator('test/cli/verilog/t_order_comboclkloop.v'); + //testVerilator('test/cli/verilog/t_order_comboloop.v', ['BLKSEQ']); + testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']); + testVerilator('test/cli/verilog/t_order_first.v'); + testVerilator('test/cli/verilog/t_order_loop_bad.v', ['BLKSEQ'], 10); + testVerilator('test/cli/verilog/t_order_multialways.v'); + testVerilator('test/cli/verilog/t_order_multidriven.v', ['UNDRIVEN']); + //testVerilator('test/cli/verilog/t_order_quad.v'); + testVerilator('test/cli/verilog/t_order_wireloop.v', ['UNOPT']); + testVerilator('test/cli/verilog/t_mem.v'); testVerilator('test/cli/verilog/t_alw_combdly.v'); diff --git a/test/cli/verilog/t_case_huge_sub3.v b/test/cli/verilog/t_case_huge_sub3.v new file mode 100644 index 00000000..0c637498 --- /dev/null +++ b/test/cli/verilog/t_case_huge_sub3.v @@ -0,0 +1,291 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t_case_huge_sub3 (/*AUTOARG*/ + // Outputs + outr, + // Inputs + clk, index + ); + + input clk; + input [9:0] index; + output [3:0] outr; + + // ============================= + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [3:0] outr; + // End of automatics + + // ============================= + // Created from perl + //for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i, + //rand(256); }; + + // Reset cheating + initial outr = 4'b0; + + always @(posedge clk) begin + case (index[7:0]) + 8'h00: begin outr <= 4'h0; end + 8'h01: begin /*No Change*/ end + 8'h02: begin outr <= outr^index[8:5]^4'ha; end + 8'h03: begin outr <= outr^index[8:5]^4'h4; end + 8'h04: begin outr <= outr^index[8:5]^4'hd; end + 8'h05: begin outr <= outr^index[8:5]^4'h1; end + 8'h06: begin outr <= outr^index[8:5]^4'hf; end + 8'h07: begin outr <= outr^index[8:5]^4'he; end + 8'h08: begin outr <= outr^index[8:5]^4'h0; end + 8'h09: begin outr <= outr^index[8:5]^4'h4; end + 8'h0a: begin outr <= outr^index[8:5]^4'h5; end + 8'h0b: begin outr <= outr^index[8:5]^4'ha; end + 8'h0c: begin outr <= outr^index[8:5]^4'h2; end + 8'h0d: begin outr <= outr^index[8:5]^4'hf; end + 8'h0e: begin outr <= outr^index[8:5]^4'h5; end + 8'h0f: begin outr <= outr^index[8:5]^4'h0; end + 8'h10: begin outr <= outr^index[8:5]^4'h3; end + 8'h11: begin outr <= outr^index[8:5]^4'hb; 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end + 8'ha5: begin outr <= outr^index[8:5]^4'h3; end + 8'ha6: begin outr <= outr^index[8:5]^4'hc; end + 8'ha7: begin outr <= outr^index[8:5]^4'h2; end + 8'ha8: begin outr <= outr^index[8:5]^4'h3; end + 8'ha9: begin outr <= outr^index[8:5]^4'hd; end + 8'haa: begin outr <= outr^index[8:5]^4'h5; end + 8'hab: begin outr <= outr^index[8:5]^4'hb; end + 8'hac: begin outr <= outr^index[8:5]^4'he; end + 8'had: begin outr <= outr^index[8:5]^4'h0; end + 8'hae: begin outr <= outr^index[8:5]^4'hf; end + 8'haf: begin outr <= outr^index[8:5]^4'h9; end + 8'hb0: begin outr <= outr^index[8:5]^4'hf; end + 8'hb1: begin outr <= outr^index[8:5]^4'h7; end + 8'hb2: begin outr <= outr^index[8:5]^4'h9; end + 8'hb3: begin outr <= outr^index[8:5]^4'hf; end + 8'hb4: begin outr <= outr^index[8:5]^4'he; end + 8'hb5: begin outr <= outr^index[8:5]^4'h3; end + 8'hb6: begin outr <= outr^index[8:5]^4'he; end + 8'hb7: begin outr <= outr^index[8:5]^4'h8; end + 8'hb8: begin outr <= outr^index[8:5]^4'hf; end + 8'hb9: begin outr <= outr^index[8:5]^4'hd; end + 8'hba: begin outr <= outr^index[8:5]^4'h3; end + 8'hbb: begin outr <= outr^index[8:5]^4'h5; end + 8'hbc: begin outr <= outr^index[8:5]^4'hd; end + 8'hbd: begin outr <= outr^index[8:5]^4'ha; end + 8'hbe: begin outr <= outr^index[8:5]^4'h7; end + 8'hbf: begin outr <= outr^index[8:5]^4'he; end + 8'hc0: begin outr <= outr^index[8:5]^4'h2; end + 8'hc1: begin outr <= outr^index[8:5]^4'he; end + 8'hc2: begin outr <= outr^index[8:5]^4'h9; end + 8'hc3: begin outr <= outr^index[8:5]^4'hb; end + 8'hc4: begin outr <= outr^index[8:5]^4'h0; end + 8'hc5: begin outr <= outr^index[8:5]^4'h5; end + 8'hc6: begin outr <= outr^index[8:5]^4'h9; end + 8'hc7: begin outr <= outr^index[8:5]^4'h6; end + 8'hc8: begin outr <= outr^index[8:5]^4'ha; end + 8'hc9: begin outr <= outr^index[8:5]^4'hf; end + 8'hca: begin outr <= outr^index[8:5]^4'h3; end + 8'hcb: begin outr <= outr^index[8:5]^4'hb; end + 8'hcc: begin outr <= outr^index[8:5]^4'he; end + 8'hcd: begin outr <= outr^index[8:5]^4'h2; end + 8'hce: begin outr <= outr^index[8:5]^4'h5; end + 8'hcf: begin outr <= outr^index[8:5]^4'hf; end + 8'hd0: begin outr <= outr^index[8:5]^4'h2; end + 8'hd1: begin outr <= outr^index[8:5]^4'h9; end + 8'hd2: begin outr <= outr^index[8:5]^4'hb; end + 8'hd3: begin outr <= outr^index[8:5]^4'h8; end + 8'hd4: begin outr <= outr^index[8:5]^4'h0; end + 8'hd5: begin outr <= outr^index[8:5]^4'h2; end + 8'hd6: begin outr <= outr^index[8:5]^4'hb; end + 8'hd7: begin outr <= outr^index[8:5]^4'h2; end + 8'hd8: begin outr <= outr^index[8:5]^4'ha; end + 8'hd9: begin outr <= outr^index[8:5]^4'hf; end + 8'hda: begin outr <= outr^index[8:5]^4'h8; end + 8'hdb: begin outr <= outr^index[8:5]^4'h4; end + 8'hdc: begin outr <= outr^index[8:5]^4'he; end + 8'hdd: begin outr <= outr^index[8:5]^4'h6; end + 8'hde: begin outr <= outr^index[8:5]^4'h9; end + 8'hdf: begin outr <= outr^index[8:5]^4'h9; end + 8'he0: begin outr <= outr^index[8:5]^4'h7; end + 8'he1: begin outr <= outr^index[8:5]^4'h0; end + 8'he2: begin outr <= outr^index[8:5]^4'h9; end + 8'he3: begin outr <= outr^index[8:5]^4'h3; end + 8'he4: begin outr <= outr^index[8:5]^4'h2; end + 8'he5: begin outr <= outr^index[8:5]^4'h4; end + 8'he6: begin outr <= outr^index[8:5]^4'h5; end + 8'he7: begin outr <= outr^index[8:5]^4'h5; end + 8'he8: begin outr <= outr^index[8:5]^4'hf; end + 8'he9: begin outr <= outr^index[8:5]^4'ha; end + 8'hea: begin outr <= outr^index[8:5]^4'hc; end + 8'heb: begin outr <= outr^index[8:5]^4'hd; end + 8'hec: begin outr <= outr^index[8:5]^4'h1; end + 8'hed: begin outr <= outr^index[8:5]^4'h5; end + 8'hee: begin outr <= outr^index[8:5]^4'h9; end + 8'hef: begin outr <= outr^index[8:5]^4'h0; end + 8'hf0: begin outr <= outr^index[8:5]^4'hd; end + 8'hf1: begin outr <= outr^index[8:5]^4'hf; end + 8'hf2: begin outr <= outr^index[8:5]^4'h4; end + 8'hf3: begin outr <= outr^index[8:5]^4'ha; end + 8'hf4: begin outr <= outr^index[8:5]^4'h8; end + 8'hf5: begin outr <= outr^index[8:5]^4'he; end + 8'hf6: begin outr <= outr^index[8:5]^4'he; end + 8'hf7: begin outr <= outr^index[8:5]^4'h1; end + 8'hf8: begin outr <= outr^index[8:5]^4'h6; end + 8'hf9: begin outr <= outr^index[8:5]^4'h0; end + 8'hfa: begin outr <= outr^index[8:5]^4'h5; end + 8'hfb: begin outr <= outr^index[8:5]^4'h1; end + 8'hfc: begin outr <= outr^index[8:5]^4'h8; end + 8'hfd: begin outr <= outr^index[8:5]^4'h6; end + 8'hfe: begin outr <= outr^index[8:5]^4'h1; end + default: begin outr <= outr^index[8:5]^4'h6; end + endcase + end +endmodule diff --git a/test/cli/verilog/t_gen_alw.v b/test/cli/verilog/t_gen_alw.v new file mode 100644 index 00000000..23b208f5 --- /dev/null +++ b/test/cli/verilog/t_gen_alw.v @@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [9:0] in = crc[9:0]; + + /*AUTOWIRE*/ + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[9:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {64'h0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module test_top (/*AUTOARG*/ + // Inputs + clk, in + ); + input clk; + input [9:0] in; + + reg a [9:0]; + integer ai; + always @* begin + for (ai=0;ai<10;ai=ai+1) begin + a[ai]=in[ai]; + end + end + + reg [1:0] b [9:0]; + integer j; + + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + for (j=0; j<10; j=j+1) begin + if (a[j]) + b[i][j] <= 1'b0; + else + b[i][j] <= 1'b1; + end + end + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_order.v b/test/cli/verilog/t_order.v new file mode 100644 index 00000000..84fbedad --- /dev/null +++ b/test/cli/verilog/t_order.v @@ -0,0 +1,107 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB + // surefire lint_off STMINI + // surefire lint_off CSEBEQ + + input clk; + + reg [7:0] a_to_clk_levm3; + reg [7:0] b_to_clk_levm1; + reg [7:0] c_com_levs10; + reg [7:0] d_to_clk_levm2; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v + wire [7:0] n_from_clk_lev2; // From a of t_order_a.v + wire [7:0] o_from_com_levs11; // From a of t_order_a.v + wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v + wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v + // End of automatics + + reg [7:0] cyc; initial cyc=0; + + t_order_a a ( + .one (8'h1), + /*AUTOINST*/ + // Outputs + .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), + .n_from_clk_lev2 (n_from_clk_lev2[7:0]), + .o_from_com_levs11 (o_from_com_levs11[7:0]), + .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), + // Inputs + .clk (clk), + .a_to_clk_levm3 (a_to_clk_levm3[7:0]), + .b_to_clk_levm1 (b_to_clk_levm1[7:0]), + .c_com_levs10 (c_com_levs10[7:0]), + .d_to_clk_levm2 (d_to_clk_levm2[7:0])); + + t_order_b b ( + /*AUTOINST*/ + // Outputs + .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), + // Inputs + .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); + + reg [7:0] o_from_com_levs12; + reg [7:0] o_from_com_levs13; + always @ (/*AS*/o_from_com_levs11) begin + o_from_com_levs12 = o_from_com_levs11 + 8'h1; + o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize + o_from_com_levs13 = o_from_com_levs12; + end + + reg sepassign_in; + // verilator lint_off UNOPTFLAT + wire [3:0] sepassign; + // verilator lint_on UNOPTFLAT + + // verilator lint_off UNOPT + assign #0.1 sepassign[0] = 0, + sepassign[1] = sepassign[2], + sepassign[2] = sepassign[3], + sepassign[3] = sepassign_in; + wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; + // verilator lint_on UNOPT + + always @ (posedge clk) begin + cyc <= cyc+8'd1; + sepassign_in <= 0; + if (cyc == 8'd1) begin + a_to_clk_levm3 <= 0; + d_to_clk_levm2 <= 1; + b_to_clk_levm1 <= 1; + c_com_levs10 <= 2; + sepassign_in <= 1; + end + if (cyc == 8'd2) begin + if (sepassign !== 4'b1110) $stop; + end + if (cyc == 8'd3) begin + + $display("%d %d %d %d",m_from_clk_lev1_r, + n_from_clk_lev2, + o_from_com_levs11, + o_from_comandclk_levs12); + + if (m_from_clk_lev1_r !== 8'h2) $stop; + if (o_subfrom_clk_lev3 !== 8'h2) $stop; + if (n_from_clk_lev2 !== 8'h2) $stop; + if (o_from_com_levs11 !== 8'h3) $stop; + if (o_from_com_levs13 !== 8'h5) $stop; + if (o_from_comandclk_levs12 !== 8'h5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_order_2d.v b/test/cli/verilog/t_order_2d.v new file mode 100644 index 00000000..35f0c35d --- /dev/null +++ b/test/cli/verilog/t_order_2d.v @@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire input_signal = crc[0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire output_signal; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .output_signal (output_signal), + // Inputs + .input_signal (input_signal)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, output_signal}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h765b2e12b25ec97b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test ( + input input_signal, + output output_signal + ); + + // bug872 + + // verilator lint_off UNOPTFLAT + wire some_signal[1:0][1:0]; + assign some_signal[0][0] = input_signal; + assign some_signal[0][1] = some_signal[0][0]; + assign some_signal[1][0] = some_signal[0][1]; + assign some_signal[1][1] = some_signal[1][0]; + assign output_signal = some_signal[1][1]; + +endmodule diff --git a/test/cli/verilog/t_order_a.v b/test/cli/verilog/t_order_a.v new file mode 100644 index 00000000..4f506203 --- /dev/null +++ b/test/cli/verilog/t_order_a.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_order_a (/*AUTOARG*/ + // Outputs + m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12, + // Inputs + clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one + ); + + input clk; + input [7:0] a_to_clk_levm3; + input [7:0] b_to_clk_levm1; + input [7:0] c_com_levs10; + input [7:0] d_to_clk_levm2; + input [7:0] one; + output [7:0] m_from_clk_lev1_r; + output [7:0] n_from_clk_lev2; + output [7:0] o_from_com_levs11; + output [7:0] o_from_comandclk_levs12; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [7:0] m_from_clk_lev1_r; + // End of automatics + + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB + + wire [7:0] a_to_clk_levm1; + wire [7:0] a_to_clk_levm2; + wire [7:0] c_com_levs11; + reg [7:0] o_from_comandclk_levs12; + wire [7:0] n_from_clk_lev2; + wire [7:0] n_from_clk_lev3; + + assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; + assign a_to_clk_levm2 = a_to_clk_levm3 + 0; + + always @ (posedge clk) begin + m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; + end + + assign c_com_levs11 = c_com_levs10 + one; + always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; + assign n_from_clk_lev2 = m_from_clk_lev1_r; + assign n_from_clk_lev3 = n_from_clk_lev2; + wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; + +endmodule diff --git a/test/cli/verilog/t_order_b.v b/test/cli/verilog/t_order_b.v new file mode 100644 index 00000000..c19f566e --- /dev/null +++ b/test/cli/verilog/t_order_b.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_order_b (/*AUTOARG*/ + // Outputs + o_subfrom_clk_lev2, + // Inputs + m_from_clk_lev1_r + ); + + input [7:0] m_from_clk_lev1_r; + output [7:0] o_subfrom_clk_lev2; + + wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r; + +endmodule diff --git a/test/cli/verilog/t_order_clkinst.v b/test/cli/verilog/t_order_clkinst.v new file mode 100644 index 00000000..ea2428e8 --- /dev/null +++ b/test/cli/verilog/t_order_clkinst.v @@ -0,0 +1,116 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // verilator lint_off COMBDLY + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + + reg c1_start; initial c1_start = 0; + wire [31:0] c1_count; + comb_loop c1 (.count(c1_count), .start(c1_start)); + + wire s2_start = (c1_count==0 && c1_start); + wire [31:0] s2_count; + seq_loop s2 (.count(s2_count), .start(s2_start)); + + wire c3_start = (s2_count[0]); + wire [31:0] c3_count; + comb_loop c3 (.count(c3_count), .start(c3_start)); + + reg [7:0] cyc; initial cyc=0; + always @ (posedge clk) begin + //$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + c1_start <= 1'b0; + end + 8'd01: begin + c1_start <= 1'b1; + end + default: ; + endcase + case (cyc) + 8'd02: begin + if (c1_count!=32'h3) $stop; + if (s2_count!=32'h3) $stop; + if (c3_count!=32'h6) $stop; + end + 8'd03: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end +endmodule + +module comb_loop (/*AUTOARG*/ + // Outputs + count, + // Inputs + start + ); + input start; + output reg [31:0] count; initial count = 0; + + reg [31:0] runnerm1, runner; initial runner = 0; + + always @ (start) begin + if (start) begin + runner = 3; + end + end + + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin + count = count + 1; + runner = runnerm1; + $write ("%m count=%d runner =%x\n",count, runnerm1); + end + end + +endmodule + +module seq_loop (/*AUTOARG*/ + // Outputs + count, + // Inputs + start + ); + input start; + output reg [31:0] count; initial count = 0; + + reg [31:0] runnerm1, runner; initial runner = 0; + + always @ (start) begin + if (start) begin + runner <= 3; + end + end + + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin + count = count + 1; + runner <= runnerm1; + $write ("%m count=%d runner<=%x\n",count, runnerm1); + end + end + +endmodule diff --git a/test/cli/verilog/t_order_comboclkloop.v b/test/cli/verilog/t_order_comboclkloop.v new file mode 100644 index 00000000..e750675a --- /dev/null +++ b/test/cli/verilog/t_order_comboclkloop.v @@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // verilator lint_off BLKANDNBLK + // verilator lint_off COMBDLY + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off MULTIDRIVEN + + reg [31:0] runnerm1, runner; initial runner = 0; + reg [31:0] runcount; initial runcount = 0; + reg [31:0] clkrun; initial clkrun = 0; + reg [31:0] clkcount; initial clkcount = 0; + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + reg run0; + always @ (/*AS*/runnerm1) begin + if ((runner & 32'hf)!=0) begin + runcount = runcount + 1; + runner = runnerm1; + $write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1); + end + run0 = (runner[8:4]!=0 && runner[3:0]==0); + end + + always @ (posedge run0) begin + // Do something that forces another combo run + clkcount <= clkcount + 1; + runner[8:4] <= runner[8:4] - 1; + runner[3:0] <= 3; + $write ("[%0t] posedge runner=%0x\n", $time, runner); + end + + reg [7:0] cyc; initial cyc=0; + always @ (posedge clk) begin + $write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount); + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin + runner <= 0; + end + 8'd01: begin + runner <= 32'h35; + end + default: ; + endcase + case (cyc) + 8'd02: begin + if (runcount!=32'he) $stop; + if (clkcount!=32'h3) $stop; + end + 8'd03: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + end +endmodule diff --git a/test/cli/verilog/t_order_comboloop.v b/test/cli/verilog/t_order_comboloop.v new file mode 100644 index 00000000..b852991d --- /dev/null +++ b/test/cli/verilog/t_order_comboloop.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + reg [31:0] runner; initial runner = 5; + reg [31:0] runnerm1; + reg [59:0] runnerq; + reg [89:0] runnerw; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin +`ifdef verilator + if (runner != 0) $stop; // Initial settlement failed +`endif + end + if (cyc==2) begin + runner = 20; + runnerq = 60'h0; + runnerw = 90'h0; + end + if (cyc==3) begin + if (runner != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + // This forms a "loop" where we keep going through the always till runner=0 + // This isn't "regular" beh code, but insures our change detection is working properly + always @ (/*AS*/runner) begin + runnerm1 = runner - 32'd1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin + runner = runnerm1; + runnerq = runnerq - 60'd1; + runnerw = runnerw - 90'd1; + $write ("[%0t] runner=%d\n", $time, runner); + end + end + +endmodule diff --git a/test/cli/verilog/t_order_doubleloop.v b/test/cli/verilog/t_order_doubleloop.v new file mode 100644 index 00000000..d8e17290 --- /dev/null +++ b/test/cli/verilog/t_order_doubleloop.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + // verilator lint_off MULTIDRIVEN + // verilator lint_off BLKANDNBLK + + reg [31:0] comcnt; + reg [31:0] dlycnt; initial dlycnt=0; + reg [31:0] lastdlycnt; initial lastdlycnt = 0; + + reg [31:0] comrun; initial comrun = 0; + reg [31:0] comrunm1; + reg [31:0] dlyrun; initial dlyrun = 0; + reg [31:0] dlyrunm1; + always @ (posedge clk) begin + $write("[%0t] cyc %d\n",$time,cyc); + cyc <= cyc + 1; + if (cyc==2) begin + // Test # of iters + lastdlycnt = 0; + comcnt = 0; + dlycnt <= 0; + end + if (cyc==3) begin + dlyrun <= 5; + dlycnt <= 0; + end + if (cyc==4) begin + comrun = 4; + end + end + always @ (negedge clk) begin + if (cyc==5) begin + $display("%d %d\n", dlycnt, comcnt); + if (dlycnt != 32'd5) $stop; + if (comcnt != 32'd19) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // This forms a "loop" where we keep going through the always till comrun=0 + reg runclk; initial runclk = 1'b0; + always @ (/*AS*/comrunm1 or dlycnt) begin + if (lastdlycnt != dlycnt) begin + comrun = 3; + $write ("[%0t] comrun=%0d start\n", $time, comrun); + end + else if (comrun > 0) begin + comrun = comrunm1; + if (comrunm1==1) begin + runclk = 1; + $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); + end + else $write ("[%0t] comrun=%0d\n", $time, comrun); + end + lastdlycnt = dlycnt; + end + + always @ (/*AS*/comrun) begin + if (comrun!=0) begin + comrunm1 = comrun - 32'd1; + comcnt = comcnt + 32'd1; + $write("[%0t] comcnt=%0d\n",$time,comcnt); + end + end + + // This forms a "loop" where we keep going through the always till dlyrun=0 + reg runclkrst; + always @ (posedge runclk) begin + runclkrst <= 1; + $write ("[%0t] runclk\n", $time); + if (dlyrun > 0) begin + dlyrun <= dlyrun - 32'd1; + dlycnt <= dlycnt + 32'd1; + $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); + end + end + + always @* begin + if (runclkrst) begin + $write ("[%0t] runclk reset\n", $time); + runclkrst = 0; + runclk = 0; + end + end + +endmodule diff --git a/test/cli/verilog/t_order_first.v b/test/cli/verilog/t_order_first.v new file mode 100644 index 00000000..645d1333 --- /dev/null +++ b/test/cli/verilog/t_order_first.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + fastclk + ); + input fastclk; + + t_netlist tnetlist + (.also_fastclk (fastclk), + /*AUTOINST*/ + // Inputs + .fastclk (fastclk)); + +endmodule + +module t_netlist (/*AUTOARG*/ + // Inputs + fastclk, also_fastclk + ); + + // surefire lint_off ASWEMB + + input fastclk; + input also_fastclk; + integer _mode; initial _mode = 0; + + // This entire module should optimize to nearly nothing... + + // verilator lint_off UNOPTFLAT + reg [4:0] a,a2,b,c,d,e; + // verilator lint_on UNOPTFLAT + + initial a=5'd1; + + always @ (posedge fastclk) begin + b <= a+5'd1; + c <= b+5'd1; // Better for ordering if this moves before previous statement + end + + // verilator lint_off UNOPT + always @ (d or /*AS*/a or c) begin + e = d+5'd1; + a2 = a+5'd1; // This can be pulled out of the middle of the always + d = c+5'd1; // Better for ordering if this moves before previous statement + end + // verilator lint_on UNOPT + + always @ (posedge also_fastclk) begin + if (_mode==5) begin + if (a2 != 5'd2) $stop; + if (e != 5'd5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + _mode <= _mode + 1; + end + +endmodule diff --git a/test/cli/verilog/t_order_loop_bad.v b/test/cli/verilog/t_order_loop_bad.v new file mode 100644 index 00000000..231c2d0c --- /dev/null +++ b/test/cli/verilog/t_order_loop_bad.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Non-cutable edge in loop +// +// This code (stripped down from a much larger application) has a loop between +// the use of ready in the first two always blocks. However it should +// trivially trigger the $write on the first clk posedge. +// +// This is a regression test against issue 513. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg ready; + + initial begin + ready = 1'b0; + end + + always @(posedge ready) begin + if ((ready === 1'b1)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always @(posedge ready) begin + if ((ready === 1'b0)) begin + ready = 1'b1 ; + end + end + + always @(posedge clk) begin + ready = 1'b1; + end + +endmodule diff --git a/test/cli/verilog/t_order_multialways.v b/test/cli/verilog/t_order_multialways.v new file mode 100644 index 00000000..23e1626d --- /dev/null +++ b/test/cli/verilog/t_order_multialways.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [31:0] in_a; + reg [31:0] in_b; + + reg [31:0] e,f,g,h; + + always @ (/*AS*/in_a) begin + e = in_a; + f = {e[15:0], e[31:16]}; + g = {f[15:0], f[31:16]}; + h = {g[15:0], g[31:16]}; + end + + // verilator lint_off UNOPTFLAT + reg [31:0] e2,f2,g2,h2; + always @ (/*AS*/f2) begin + h2 = {g2[15:0], g2[31:16]}; + g2 = {f2[15:0], f2[31:16]}; + end + always @ (/*AS*/in_a) begin + f2 = {e2[15:0], e2[31:16]}; + e2 = in_a; + end + // verilator lint_on UNOPTFLAT + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x\n", cyc, h, h2); + if (h != h2) $stop; + if (cyc==1) begin + in_a <= 32'h89a14fab; + in_b <= 32'h7ab512fa; + end + if (cyc==2) begin + in_a <= 32'hf4c11a42; + in_b <= 32'h359967c6; + if (h != 32'h4fab89a1) $stop; + end + if (cyc==3) begin + if (h != 32'h1a42f4c1) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_order_multidriven.v b/test/cli/verilog/t_order_multidriven.v new file mode 100644 index 00000000..1a2ff596 --- /dev/null +++ b/test/cli/verilog/t_order_multidriven.v @@ -0,0 +1,192 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Ted Campbell. + +//With MULTI_CLK defined shows bug, without it is hidden +`define MULTI_CLK + +//bug634 + +module t ( + input i_clk_wr, + input i_clk_rd + ); + + wire wr$wen; + wire [7:0] wr$addr; + wire [7:0] wr$wdata; + wire [7:0] wr$rdata; + + wire rd$wen; + wire [7:0] rd$addr; + wire [7:0] rd$wdata; + wire [7:0] rd$rdata; + + wire clk_wr; + wire clk_rd; + + `ifdef MULTI_CLK + assign clk_wr = i_clk_wr; + assign clk_rd = i_clk_rd; + `else + assign clk_wr = i_clk_wr; + assign clk_rd = i_clk_wr; + `endif + + FooWr u_wr ( + .i_clk ( clk_wr ), + + .o_wen ( wr$wen ), + .o_addr ( wr$addr ), + .o_wdata ( wr$wdata ), + .i_rdata ( wr$rdata ) + ); + + FooRd u_rd ( + .i_clk ( clk_rd ), + + .o_wen ( rd$wen ), + .o_addr ( rd$addr ), + .o_wdata ( rd$wdata ), + .i_rdata ( rd$rdata ) + ); + + FooMem u_mem ( + .iv_clk ( {clk_wr, clk_rd } ), + .iv_wen ( {wr$wen, rd$wen } ), + .iv_addr ( {wr$addr, rd$addr } ), + .iv_wdata ( {wr$wdata,rd$wdata} ), + .ov_rdata ( {wr$rdata,rd$rdata} ) + ); + +endmodule + + +// Memory Writer +module FooWr( + input i_clk, + + output o_wen, + output [7:0] o_addr, + output [7:0] o_wdata, + input [7:0] i_rdata + ); + + reg [7:0] cnt = 0; + + // Count [0,200] + always @( posedge i_clk ) + if ( cnt < 8'd50 ) + cnt <= cnt + 8'd1; + + // Write addr in (10,30) if even + assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 ); + assign o_addr = cnt; + assign o_wdata = cnt; + +endmodule + + +// Memory Reader +module FooRd( + input i_clk, + + output o_wen, + output [7:0] o_addr, + output [7:0] o_wdata, + input [7:0] i_rdata + ); + + reg [7:0] cnt = 0; + reg [7:0] addr_r; + reg en_r; + + // Count [0,200] + always @( posedge i_clk ) + if ( cnt < 8'd200 ) + cnt <= cnt + 8'd1; + + // Read data + assign o_wen = 0; + assign o_addr = cnt - 8'd100; + + // Track issued read + always @( posedge i_clk ) + begin + addr_r <= o_addr; + en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 ); + end + + // Display to console 100 cycles after writer + always @( negedge i_clk ) + if ( en_r ) begin +`ifdef TEST_VERBOSE + $display( "MEM[%x] == %x", addr_r, i_rdata ); +`endif + if (addr_r != i_rdata) $stop; + end + +endmodule + + +// Multi-port memory abstraction +module FooMem( + input [2 -1:0] iv_clk, + input [2 -1:0] iv_wen, + input [2*8-1:0] iv_addr, + input [2*8-1:0] iv_wdata, + output [2*8-1:0] ov_rdata + ); + + FooMemImpl u_impl ( + .a_clk ( iv_clk [0*1+:1] ), + .a_wen ( iv_wen [0*1+:1] ), + .a_addr ( iv_addr [0*8+:8] ), + .a_wdata ( iv_wdata[0*8+:8] ), + .a_rdata ( ov_rdata[0*8+:8] ), + + .b_clk ( iv_clk [1*1+:1] ), + .b_wen ( iv_wen [1*1+:1] ), + .b_addr ( iv_addr [1*8+:8] ), + .b_wdata ( iv_wdata[1*8+:8] ), + .b_rdata ( ov_rdata[1*8+:8] ) + ); + +endmodule + + +// Dual-Port L1 Memory Implementation +module FooMemImpl( + input a_clk, + input a_wen, + input [7:0] a_addr, + input [7:0] a_wdata, + output [7:0] a_rdata, + + input b_clk, + input b_wen, + input [7:0] b_addr, + input [7:0] b_wdata, + output [7:0] b_rdata + ); + + /* verilator lint_off MULTIDRIVEN */ + reg [7:0] mem[0:255]; + /* verilator lint_on MULTIDRIVEN */ + + always @( posedge a_clk ) + if ( a_wen ) + mem[a_addr] <= a_wdata; + + always @( posedge b_clk ) + if ( b_wen ) + mem[b_addr] <= b_wdata; + + always @( posedge a_clk ) + a_rdata <= mem[a_addr]; + + always @( posedge b_clk ) + b_rdata <= mem[b_addr]; + +endmodule diff --git a/test/cli/verilog/t_order_quad.v b/test/cli/verilog/t_order_quad.v new file mode 100644 index 00000000..37ede648 --- /dev/null +++ b/test/cli/verilog/t_order_quad.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +//bug 762 +module t(a0, y); + input [3:0] a0; + output [44:0] y; + + assign y[40] = 0; + assign y[30] = 0; + // verilator lint_off UNOPTFLAT + assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 }; + +endmodule diff --git a/test/cli/verilog/t_order_wireloop.v b/test/cli/verilog/t_order_wireloop.v new file mode 100644 index 00000000..b1156cf8 --- /dev/null +++ b/test/cli/verilog/t_order_wireloop.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + bar + ); + + wire foo; + output bar; + + // Oh dear. + assign foo = bar; + assign bar = foo; + +endmodule