From b9a0de6cacb45041a46530fad8a5f38c932535de Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Wed, 7 Jul 2021 11:06:22 -0500 Subject: [PATCH] verilog: test updates, source locations, labels, Silice --- doc/notes.txt | 13 +- package-lock.json | 74 ++++++ package.json | 7 +- presets/verilog/cpu6502.v | 21 +- presets/verilog/font_cp437_8x8.v | 7 +- src/common/hdl/hdlruntime.ts | 7 +- src/common/hdl/hdltypes.ts | 8 +- src/common/hdl/hdlwasm.ts | 90 ++++--- src/common/hdl/vxmlparser.ts | 77 ++++-- src/platform/verilog.ts | 28 +- src/worker/workermain.ts | 21 +- test/cli/testverilog.js | 87 ++++--- test/cli/verilog/t_EXAMPLE.v | 97 +++++++ test/cli/verilog/t_dynarray_param.v | 54 ---- test/cli/verilog/t_gate_elim.v | 122 +++++++++ test/cli/verilog/t_gate_lvalue_const.v | 66 +++++ test/cli/verilog/t_gated_clk_1.v | 56 ++++ test/cli/verilog/t_gen_cond_bitrange.v | 139 ++++++++++ test/cli/verilog/t_gen_cond_const.v | 72 ++++++ test/cli/verilog/t_gen_div0.v | 39 +++ test/cli/verilog/t_gen_for.v | 173 +++++++++++++ test/cli/verilog/t_gen_for0.v | 48 ++++ test/cli/verilog/t_gen_for1.v | 84 ++++++ test/cli/verilog/t_gen_for_interface.v | 32 +++ test/cli/verilog/t_gen_for_overlap.v | 50 ++++ test/cli/verilog/t_gen_for_shuffle.v | 80 ++++++ test/cli/verilog/t_gen_inc.v | 109 ++++++++ test/cli/verilog/t_gen_index.v | 72 ++++++ test/cli/verilog/t_gen_intdot2.v | 161 ++++++++++++ test/cli/verilog/t_gen_local.v | 36 +++ test/cli/verilog/t_inside_wild.v | 84 ++++++ test/cli/verilog/t_inst_dff.v | 132 ++++++++++ test/cli/verilog/t_inst_mism.v | 42 +++ test/cli/verilog/t_inst_missing.v | 18 ++ test/cli/verilog/t_inst_mnpipe.v | 72 ++++++ test/cli/verilog/t_inst_port_array.v | 49 ++++ test/cli/verilog/t_inst_prepost.v | 33 +++ test/cli/verilog/t_inst_signed.v | 66 +++++ test/cli/verilog/t_inst_signed1.v | 52 ++++ test/cli/verilog/t_inst_slice.v | 85 +++++++ test/cli/verilog/t_inst_slice_part_select.v | 93 +++++++ test/cli/verilog/t_inst_tree.v | 87 +++++++ test/cli/verilog/t_interface1.v | 46 ++++ test/cli/verilog/t_interface1_modport.v | 57 +++++ test/cli/verilog/t_interface_ar2a.v | 30 +++ test/cli/verilog/t_interface_ar2b.v | 35 +++ test/cli/verilog/t_interface_gen.v | 88 +++++++ test/cli/verilog/t_interface_gen12.v | 30 +++ test/cli/verilog/t_interface_gen4.v | 59 +++++ test/cli/verilog/t_interface_gen5.v | 61 +++++ test/cli/verilog/t_interface_gen6.v | 57 +++++ test/cli/verilog/t_interface_modport_import.v | 59 +++++ test/cli/verilog/t_interface_modportlist.v | 24 ++ test/cli/verilog/t_interface_param1.v | 52 ++++ .../verilog/t_interface_parameter_access.v | 141 +++++++++++ test/cli/verilog/t_interface_twod.v | 48 ++++ test/cli/verilog/t_langext_1.v | 51 ++++ test/cli/verilog/t_langext_2.v | 56 ++++ test/cli/verilog/t_langext_3.v | 22 ++ test/cli/verilog/t_math_cmp.v | 169 +++++++++++++ test/cli/verilog/t_math_concat.v | 75 ++++++ test/cli/verilog/t_math_concat0.v | 88 +++++++ test/cli/verilog/t_math_concat64.v | 131 ++++++++++ test/cli/verilog/t_math_cond_clean.v | 95 +++++++ test/cli/verilog/t_math_eq.v | 93 +++++++ test/cli/verilog/t_math_equal.v | 74 ++++++ test/cli/verilog/t_math_imm.v | 114 +++++++++ test/cli/verilog/t_math_imm2.v | 43 ++++ test/cli/verilog/t_math_msvc_64.v | 75 ++++++ test/cli/verilog/t_math_mul.v | 72 ++++++ test/cli/verilog/t_math_pick.v | 83 ++++++ test/cli/verilog/t_math_real_public.v | 19 ++ test/cli/verilog/t_math_red.v | 65 +++++ test/cli/verilog/t_math_repl.v | 110 ++++++++ test/cli/verilog/t_math_reverse.v | 83 ++++++ test/cli/verilog/t_math_shift.v | 239 ++++++++++++++++++ test/cli/verilog/t_math_shift_extend.v | 64 +++++ test/cli/verilog/t_math_shift_rep.v | 78 ++++++ test/cli/verilog/t_math_shift_sel.v | 88 +++++++ test/cli/verilog/t_math_shiftrs.v | 57 +++++ test/cli/verilog/t_math_sign_extend.v | 132 ++++++++++ test/cli/verilog/t_math_signed2.v | 67 +++++ test/cli/verilog/t_math_signed3.v | 101 ++++++++ test/cli/verilog/t_math_signed4.v | 141 +++++++++++ test/cli/verilog/t_math_signed6.v | 37 +++ test/cli/verilog/t_math_signed7.v | 45 ++++ test/cli/verilog/t_math_signed_wire.v | 54 ++++ test/cli/verilog/t_math_strwidth.v | 20 ++ test/cli/verilog/t_math_svl2.v | 41 +++ test/cli/verilog/t_math_swap.v | 165 ++++++++++++ test/cli/verilog/t_math_tri.v | 22 ++ test/cli/verilog/t_math_vliw.v | 104 ++++++++ test/cli/verilog/t_math_width.v | 59 +++++ test/cli/verilog/t_math_yosys.v | 84 ++++++ test/cli/verilog/t_mem_banks.v | 73 ++++++ test/cli/verilog/t_mem_cond.v | 31 +++ test/cli/verilog/t_mem_fifo.v | 111 ++++++++ test/cli/verilog/t_mem_func.v | 124 +++++++++ test/cli/verilog/t_mem_iforder.v | 103 ++++++++ test/cli/verilog/t_mem_multi_io.v | 63 +++++ test/cli/verilog/t_mem_multi_io2.v | 40 +++ test/cli/verilog/t_mem_multidim.v | 100 ++++++++ test/cli/verilog/t_mem_packed.v | 180 +++++++++++++ test/cli/verilog/t_mem_packed_assign.v | 39 +++ test/cli/verilog/t_mem_shift.v | 62 +++++ test/cli/verilog/t_mem_slice.v | 124 +++++++++ test/cli/verilog/t_mem_slot.v | 26 ++ test/cli/verilog/t_mem_twoedge.v | 118 +++++++++ test/cli/verilog/t_mod_dup_ign.v | 24 ++ test/cli/verilog/t_mod_interface_array0.v | 64 +++++ test/cli/verilog/t_mod_interface_array1.v | 66 +++++ test/cli/verilog/t_mod_interface_array2.v | 65 +++++ test/cli/verilog/t_mod_recurse1.v | 36 +++ test/cli/verilog/t_mod_uselib.v | 18 ++ test/cli/verilog/t_multitop1s.v | 13 + test/cli/verilog/t_multitop_sig.v | 33 +++ .../verilog/t_no_sel_assign_merge_in_cpp.v | 14 + test/cli/verilog/t_opt_table_enum.v | 45 ++++ test/cli/verilog/t_opt_table_packed_array.v | 38 +++ test/cli/verilog/t_opt_table_same.v | 51 ++++ test/cli/verilog/t_opt_table_signed.v | 38 +++ test/cli/verilog/t_opt_table_sparse.v | 40 +++ test/cli/verilog/t_optm_if_array.v | 52 ++++ test/cli/verilog/t_optm_if_cond.v | 57 +++++ test/cli/verilog/t_optm_redor.v | 84 ++++++ test/cli/verilog/t_order.v | 108 -------- test/cli/verilog/t_param.v | 76 ++++++ test/cli/verilog/t_param_array.v | 87 +++++++ test/cli/verilog/t_param_array2.v | 22 ++ test/cli/verilog/t_param_array3.v | 31 +++ test/cli/verilog/t_param_array4.v | 42 +++ test/cli/verilog/t_param_array5.v | 39 +++ test/cli/verilog/t_param_avec.v | 39 +++ test/cli/verilog/t_param_bit_sel.v | 33 +++ test/cli/verilog/t_param_bracket.v | 18 ++ test/cli/verilog/t_param_ceil.v | 56 ++++ test/cli/verilog/t_param_chain.v | 37 +++ test/cli/verilog/t_param_const_part.v | 28 ++ test/cli/verilog/t_param_ddeep_width.v | 30 +++ test/cli/verilog/t_param_default.v | 20 ++ test/cli/verilog/t_param_first_b.v | 22 ++ test/cli/verilog/t_param_func.v | 34 +++ test/cli/verilog/t_param_func2.v | 52 ++++ test/cli/verilog/t_param_if_blk.v | 141 +++++++++++ test/cli/verilog/t_param_local.v | 29 +++ test/cli/verilog/t_param_mem_attr.v | 42 +++ test/cli/verilog/t_param_module.v | 56 ++++ test/cli/verilog/t_param_no_parentheses.v | 75 ++++++ test/cli/verilog/t_param_package.v | 26 ++ test/cli/verilog/t_param_real.v | 27 ++ test/cli/verilog/t_param_real2.v | 37 +++ test/cli/verilog/t_param_repl.v | 51 ++++ test/cli/verilog/t_param_seg.v | 29 +++ test/cli/verilog/t_param_sel.v | 94 +++++++ test/cli/verilog/t_param_shift.v | 31 +++ test/cli/verilog/t_param_type.v | 93 +++++++ test/cli/verilog/t_param_type2.v | 41 +++ test/cli/verilog/t_param_type3.v | 60 +++++ test/cli/verilog/t_param_unreachable.v | 34 +++ test/cli/verilog/t_param_value.v | 64 +++++ test/cli/verilog/t_param_while.v | 34 +++ test/cli/verilog/t_param_wide_io.v | 20 ++ test/cli/verilog/t_param_width.v | 38 +++ test/cli/verilog/t_parse_delay.v | 21 ++ test/cli/verilog/t_past.v | 106 ++++++++ test/cli/verilog/t_past_funcs.v | 105 ++++++++ test/cli/verilog/t_pp_display.v | 69 +++++ test/cli/verilog/t_pp_pragmas.v | 61 +++++ test/cli/verilog/t_real_param.v | 36 +++ test/cli/verilog/t_reloop_offset.v | 50 ++++ test/cli/verilog/t_rnd.v | 49 ++++ test/cli/verilog/t_runflag.v | 12 + test/cli/verilog/t_sc_names.v | 11 + test/cli/verilog/t_select_2d.v | 78 ++++++ test/cli/verilog/t_select_bound1.v | 92 +++++++ test/cli/verilog/t_select_bound2.v | 92 +++++++ test/cli/verilog/t_select_index.v | 49 ++++ test/cli/verilog/t_select_index2.v | 37 +++ test/cli/verilog/t_select_lhs_oob.v | 93 +++++++ test/cli/verilog/t_select_lhs_oob2.v | 142 +++++++++++ test/cli/verilog/t_select_little.v | 75 ++++++ test/cli/verilog/t_select_little_pack.v | 29 +++ test/cli/verilog/t_select_param.v | 18 ++ test/cli/verilog/t_select_plus_mul_pow2.v | 54 ++++ test/cli/verilog/t_select_runtime_range.v | 76 ++++++ test/cli/verilog/t_select_set.v | 50 ++++ test/cli/verilog/t_slice_cond.v | 39 +++ test/cli/verilog/t_slice_init.v | 60 +++++ test/cli/verilog/t_static_elab.v | 52 ++++ test/cli/verilog/t_table_fsm.v | 160 ++++++++++++ test/cli/verilog/t_time_literals.v | 32 +++ test/cli/verilog/t_tri_array_bufif.v | 118 +++++++++ test/cli/verilog/t_tri_array_pull.v | 44 ++++ test/cli/verilog/t_tri_eqcase.v | 129 ++++++++++ test/cli/verilog/t_tri_inz.v | 18 ++ test/cli/verilog/t_tri_pull01.v | 94 +++++++ test/cli/verilog/t_tri_select.v | 44 ++++ test/cli/verilog/t_type.v | 24 ++ test/cli/verilog/t_type_param.v | 112 ++++++++ test/cli/verilog/t_unbounded.v | 23 ++ test/cli/verilog/t_unconnected.v | 46 ++++ test/cli/verilog/t_uniqueif.v | 112 ++++++++ test/cli/verilog/t_unopt_array.v | 91 +++++++ test/cli/verilog/t_unopt_combo.v | 142 +++++++++++ test/cli/verilog/t_unopt_converge.v | 26 ++ test/cli/verilog/t_unopt_converge_initial.v | 26 ++ test/cli/verilog/t_unoptflat_simple.v | 33 +++ test/cli/verilog/t_unoptflat_simple_2.v | 32 +++ test/cli/verilog/t_unoptflat_simple_3.v | 80 ++++++ test/cli/verilog/t_unpacked_slice.v | 57 +++++ test/cli/verilog/t_unroll_forfor.v | 35 +++ test/cli/verilog/t_unroll_genf.v | 30 +++ test/cli/verilog/t_vams_basic.v | 48 ++++ test/cli/verilog/t_var_assign_landr.v | 91 +++++++ test/cli/verilog/t_var_const.v | 27 ++ test/cli/verilog/t_var_dup2.v | 15 ++ test/cli/verilog/t_var_dup3.v | 29 +++ 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create mode 100644 test/cli/verilog/t_var_overzero.v create mode 100644 test/cli/verilog/t_var_pinsizes.v create mode 100644 test/cli/verilog/t_var_set_link.v create mode 100644 test/cli/verilog/t_var_tieout.v create mode 100644 test/cli/verilog/t_var_types.v create mode 100644 test/cli/verilog/t_var_vec_sel.v create mode 100644 test/cli/verilog/t_var_xref_gen.v create mode 100644 test/cli/verilog/t_waiveroutput.v create mode 100644 test/cli/verilog/t_wire_types.v create mode 100644 test/cli/verilog/t_x_assign.v diff --git a/doc/notes.txt b/doc/notes.txt index f3d477ec..ba6d7c17 100644 --- a/doc/notes.txt +++ b/doc/notes.txt @@ -99,16 +99,21 @@ TODO: - verilog debugging/reloading makes it slow - why loadState() on verilog kill perf? - quantify verilog "graph iterations" - - toolbar overlaps scope - CPU debugging - use $readmem for inline asm programs? - can't add control instructions b/c of split - bad error msg if >2 moduels and top module doesn't match filename - separate Scope View - Audio doesn't work if clock != default - - change the input values for a module? - - Silice rototexture.ice example bitmap corrupted? - - scope: zoom in on cursor +- Verilog WASM not yet supported: + - wide numbers > 64 bits (and in scope view) + - multiple modules instances + - structs + - other $funcs + - multidim arrays + - optimize trace log w/ wasm buffer + - yosys compatibility + - single-stepping vector games makes screen fade - break on stack overflow, illegal op, bad access, BRK, etc - show in scope instead? diff --git a/package-lock.json b/package-lock.json index c727a8c1..a61f7d6a 100644 --- a/package-lock.json +++ b/package-lock.json @@ -27,6 +27,7 @@ "btoa": "^1.2.x", "chromedriver": "^90.0.1", "clipboard": "^2.0.6", + "command-exists": "^1.2.9", "electron": "^9.4.0", "electron-packager": "^15.2.0", "file-saver": "^2.0.5", @@ -37,6 +38,7 @@ "localforage": "^1.9.0", "lzg": "^1.0.x", "mocha": "^7.2.0", + "mocha-simple-html-reporter": "^2.0.0", "mousetrap": "^1.6.5", "nightwatch": "^1.6.4", "octokat": "^0.10.0", @@ -1246,6 +1248,12 @@ "node": ">= 0.8" } }, + "node_modules/command-exists": { + "version": "1.2.9", + "resolved": "https://registry.npmjs.org/command-exists/-/command-exists-1.2.9.tgz", + "integrity": "sha512-LTQ/SGc+s0Xc0Fu5WaKnR0YiygZkm9eKFvyS+fRsU7/ZWFF8ykFM6Pc9aCVf1+xasOOZpO3BAVgVrKvsqKHV7w==", + "dev": true + }, "node_modules/commander": { "version": "5.1.0", "resolved": "https://registry.npmjs.org/commander/-/commander-5.1.0.tgz", @@ -4566,6 +4574,18 @@ "url": "https://opencollective.com/mochajs" } }, + "node_modules/mocha-simple-html-reporter": { + "version": "2.0.0", + "resolved": "https://registry.npmjs.org/mocha-simple-html-reporter/-/mocha-simple-html-reporter-2.0.0.tgz", + "integrity": "sha512-adaJlWWDoAT1OMjsjo6uOOOaMwmGf8ZQEXVoUdlD34Xjgz4M50FW7fe9ksl6UFLoisSB9Ai49LzRh6LuId1+cA==", + "dev": true, + "dependencies": { + "pretty-ms": "7.0.1" + }, + "engines": { + "node": ">= 10.12.0" + } + }, "node_modules/mocha/node_modules/ansi-regex": { "version": "4.1.0", "resolved": "https://registry.npmjs.org/ansi-regex/-/ansi-regex-4.1.0.tgz", @@ -5705,6 +5725,15 @@ "node": ">=0.10.0" } }, + "node_modules/parse-ms": { + "version": "2.1.0", + "resolved": "https://registry.npmjs.org/parse-ms/-/parse-ms-2.1.0.tgz", + "integrity": "sha512-kHt7kzLoS9VBZfUsiKjv43mr91ea+U05EyKkEtqp7vNbHxmaVuEqN7XxeEVnGrMtYOAxGrDElSi96K7EgO1zCA==", + "dev": true, + "engines": { + "node": ">=6" + } + }, "node_modules/parse5": { "version": "5.1.0", "resolved": "https://registry.npmjs.org/parse5/-/parse5-5.1.0.tgz", @@ -5886,6 +5915,21 @@ "node": ">=4" } }, + "node_modules/pretty-ms": { + "version": "7.0.1", + "resolved": "https://registry.npmjs.org/pretty-ms/-/pretty-ms-7.0.1.tgz", + "integrity": "sha512-973driJZvxiGOQ5ONsFhOF/DtzPMOMtgC11kCpUrPGMTgqp2q/1gwzCquocrN33is0VZ5GFHXZYMM9l6h67v2Q==", + "dev": true, + "dependencies": { + "parse-ms": "^2.1.0" + }, + "engines": { + "node": ">=10" + }, + "funding": { + "url": "https://github.com/sponsors/sindresorhus" + } + }, "node_modules/process-nextick-args": { "version": "2.0.1", "resolved": "https://registry.npmjs.org/process-nextick-args/-/process-nextick-args-2.0.1.tgz", @@ -8644,6 +8688,12 @@ "delayed-stream": "~1.0.0" } }, + "command-exists": { + "version": "1.2.9", + "resolved": "https://registry.npmjs.org/command-exists/-/command-exists-1.2.9.tgz", + "integrity": "sha512-LTQ/SGc+s0Xc0Fu5WaKnR0YiygZkm9eKFvyS+fRsU7/ZWFF8ykFM6Pc9aCVf1+xasOOZpO3BAVgVrKvsqKHV7w==", + "dev": true + }, "commander": { "version": "5.1.0", "resolved": "https://registry.npmjs.org/commander/-/commander-5.1.0.tgz", @@ -11409,6 +11459,15 @@ } } }, + "mocha-simple-html-reporter": { + "version": "2.0.0", + "resolved": "https://registry.npmjs.org/mocha-simple-html-reporter/-/mocha-simple-html-reporter-2.0.0.tgz", + "integrity": "sha512-adaJlWWDoAT1OMjsjo6uOOOaMwmGf8ZQEXVoUdlD34Xjgz4M50FW7fe9ksl6UFLoisSB9Ai49LzRh6LuId1+cA==", + "dev": true, + "requires": { + "pretty-ms": "7.0.1" + } + }, "mousetrap": { "version": "1.6.5", "resolved": "https://registry.npmjs.org/mousetrap/-/mousetrap-1.6.5.tgz", @@ -12193,6 +12252,12 @@ "error-ex": "^1.2.0" } }, + "parse-ms": { + "version": "2.1.0", + "resolved": "https://registry.npmjs.org/parse-ms/-/parse-ms-2.1.0.tgz", + "integrity": "sha512-kHt7kzLoS9VBZfUsiKjv43mr91ea+U05EyKkEtqp7vNbHxmaVuEqN7XxeEVnGrMtYOAxGrDElSi96K7EgO1zCA==", + "dev": true + }, "parse5": { "version": "5.1.0", "resolved": "https://registry.npmjs.org/parse5/-/parse5-5.1.0.tgz", @@ -12320,6 +12385,15 @@ "integrity": "sha1-6SQ0v6XqjBn0HN/UAddBo8gZ2Jc=", "dev": true }, + "pretty-ms": { + "version": "7.0.1", + "resolved": "https://registry.npmjs.org/pretty-ms/-/pretty-ms-7.0.1.tgz", + "integrity": "sha512-973driJZvxiGOQ5ONsFhOF/DtzPMOMtgC11kCpUrPGMTgqp2q/1gwzCquocrN33is0VZ5GFHXZYMM9l6h67v2Q==", + "dev": true, + "requires": { + "parse-ms": "^2.1.0" + } + }, "process-nextick-args": { "version": "2.0.1", "resolved": "https://registry.npmjs.org/process-nextick-args/-/process-nextick-args-2.0.1.tgz", diff --git a/package.json b/package.json index 034e9cef..0ebdc59e 100644 --- a/package.json +++ b/package.json @@ -28,6 +28,7 @@ "btoa": "^1.2.x", "chromedriver": "^90.0.1", "clipboard": "^2.0.6", + "command-exists": "^1.2.9", "electron": "^9.4.0", "electron-packager": "^15.2.0", "file-saver": "^2.0.5", @@ -38,6 +39,7 @@ "localforage": "^1.9.0", "lzg": "^1.0.x", "mocha": "^7.2.0", + "mocha-simple-html-reporter": "^2.0.0", "mousetrap": "^1.6.5", "nightwatch": "^1.6.4", "octokat": "^0.10.0", @@ -58,9 +60,10 @@ "test": "npm run test-node", "test-one": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000", "test-node": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 test/cli", - "test-worker": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 test/cli/testworker.js", - "test-platforms": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 test/cli/testplatforms.js", "test-profile": "NODE_PATH=$(pwd) mocha --recursive --timeout 60000 --prof test/cli", + "test-worker": "NODE_PATH=$(pwd) mocha --timeout 60000 test/cli/testworker.js", + "test-platforms": "NODE_PATH=$(pwd) mocha --timeout 60000 test/cli/testplatforms.js", + "test-verilog": "NODE_PATH=$(pwd) mocha --timeout 60000 --reporter mocha-simple-html-reporter --reporter-options output=test/output/verilog.html test/cli/testverilog.js", "test-web": "nightwatch -e chrome test/web", "start": "electron .", "fuzzbasic": "jsfuzz gen/common/basic/fuzz.js ~/basic/corpus/ --versifier false", diff --git a/presets/verilog/cpu6502.v b/presets/verilog/cpu6502.v index a2a776be..8e69021c 100644 --- a/presets/verilog/cpu6502.v +++ b/presets/verilog/cpu6502.v @@ -355,7 +355,7 @@ always @* */ always @(posedge clk) if( RDY ) - PC <= PC_temp + 16'(PC_inc); + PC <= PC_temp + {15'b0, PC_inc}; /* * Address Generator @@ -1315,8 +1315,8 @@ wire temp_HC = temp_l[4] | HC9; // perform the addition as 2 separate nibble, so we get // access to the half carry flag always @* begin - temp_l = temp_logic[3:0] + temp_BI[3:0] + 5'(adder_CI); - temp_h = temp_logic[8:4] + temp_BI[7:4] + 5'(temp_HC); + temp_l = temp_logic[3:0] + temp_BI[3:0] + {4'b0,adder_CI}; + temp_h = temp_logic[8:4] + temp_BI[7:4] + {4'b0,temp_HC}; end // calculate the flags @@ -1339,7 +1339,7 @@ endmodule module cpu6502_test_top(clk, reset, AB, DI, DO, WE); input clk,reset; output reg [15:0] AB; // address bus -output var [7:0] DI; // data in, read bus +output reg [7:0] DI; // data in, read bus output wire [7:0] DO; // data out, write bus output wire WE; // write enable wire IRQ=0; // interrupt request @@ -1359,13 +1359,12 @@ wire RDY=1; // Ready signal. Pauses CPU when RDY=0 // BNE .loop // BRK initial begin - rom = '{ - 8'ha0,8'h13, - 8'h88, - 8'hd0,8'hfd, - 0,0,0, 0,0, - 0,0, 0,0, 0,0 - }; + rom[0] = 8'ha0; + rom[1] = 8'h13; + rom[2] = 8'h88; + rom[3] = 8'hd0; + rom[4] = 8'hfd; + rom[5] = 8'h00; end endmodule diff --git a/presets/verilog/font_cp437_8x8.v b/presets/verilog/font_cp437_8x8.v index e318844d..187bdce5 100644 --- a/presets/verilog/font_cp437_8x8.v +++ b/presets/verilog/font_cp437_8x8.v @@ -9,12 +9,9 @@ module font_cp437_8x8(addr, data); input [10:0] addr; output [7:0] data; - reg [7:0] bitarray[0:2047]; - assign data = bitarray[addr]; - initial begin/*{w:8,h:8,bpp:1,count:256}*/ - bitarray = '{ + localparam [7:0] bitarray[0:2047] = '{ 8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00, //0 8'h7e,8'h81,8'ha5,8'h81,8'hbd,8'h99,8'h81,8'h7e, //1 8'h7e,8'hff,8'hdb,8'hff,8'hc3,8'he7,8'hff,8'h7e, //2 @@ -272,7 +269,7 @@ module font_cp437_8x8(addr, data); 8'h00,8'h00,8'h3c,8'h3c,8'h3c,8'h3c,8'h00,8'h00, //254 8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00 //255 }; - end + endmodule `endif diff --git a/src/common/hdl/hdlruntime.ts b/src/common/hdl/hdlruntime.ts index a57a6251..85bd6536 100644 --- a/src/common/hdl/hdlruntime.ts +++ b/src/common/hdl/hdlruntime.ts @@ -1,4 +1,5 @@ +import { EmuHalt } from "../emu"; import { byteArrayToString, safe_extend } from "../util"; import { HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLExpr, HDLExtendop, HDLFuncCall, HDLModuleDef, HDLModuleRunner, HDLSourceLocation, HDLTriop, HDLUnop, HDLValue, HDLVariableDef, HDLVarRef, isArrayItem, isArrayType, isBigConstExpr, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef, isWhileop } from "./hdltypes"; @@ -10,14 +11,12 @@ interface VerilatorUnit { _change_request(state) : boolean; } -export class HDLError extends Error { +export class HDLError extends EmuHalt { obj: any; - $loc: HDLSourceLocation; constructor(obj: any, msg: string) { - super(msg); + super(msg, obj ? obj.$loc : null); Object.setPrototypeOf(this, HDLError.prototype); this.obj = obj; - if (obj && obj.$loc) this.$loc = obj.$loc; if (obj) console.log(obj); } } diff --git a/src/common/hdl/hdltypes.ts b/src/common/hdl/hdltypes.ts index 597dd9aa..3391de86 100644 --- a/src/common/hdl/hdltypes.ts +++ b/src/common/hdl/hdltypes.ts @@ -1,3 +1,4 @@ +import { SourceLocation } from "../workertypes"; export interface HDLModuleRunner { state: any; // live state or proxy object @@ -54,12 +55,9 @@ export class HDLFile { isModule: boolean; } -export interface HDLSourceLocation { - file: HDLFile; - line: number; - col?: number; +export interface HDLSourceLocation extends SourceLocation { + hdlfile: HDLFile; end_line?: number; - end_col?: number; } export interface HDLSourceObject { diff --git a/src/common/hdl/hdlwasm.ts b/src/common/hdl/hdlwasm.ts index b356819f..b7fda74d 100644 --- a/src/common/hdl/hdlwasm.ts +++ b/src/common/hdl/hdlwasm.ts @@ -1,6 +1,6 @@ import binaryen = require('binaryen'); -import { hasDataType, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFuncCall, HDLModuleDef, HDLModuleRunner, HDLSourceLocation, HDLTriop, HDLUnop, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayItem, isArrayType, isBigConstExpr, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef, isWhileop } from "./hdltypes"; +import { hasDataType, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFuncCall, HDLModuleDef, HDLModuleRunner, HDLSourceLocation, HDLSourceObject, HDLTriop, HDLUnop, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayItem, isArrayType, isBigConstExpr, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef, isWhileop } from "./hdltypes"; import { HDLError } from "./hdlruntime"; const VERILATOR_UNIT_FUNCTIONS = [ @@ -14,6 +14,7 @@ const VERILATOR_UNIT_FUNCTIONS = [ interface Options { store?: boolean; funcblock?: HDLBlock; + funcarg?: boolean; resulttype?: number; } @@ -64,7 +65,7 @@ function getArrayElementSizeFromExpr(e: HDLExpr) : number { if (hasDataType(e) && isArrayType(e.dtype)) { return getDataTypeSize(e.dtype.subtype); } else if (hasDataType(e) && isLogicType(e.dtype) && e.dtype.left > 63) { - return 4; // TODO? for wordsel + throw new HDLError(e, `elements > 64 bits not supported`); } throw new HDLError(e, `cannot figure out array element size`); } @@ -78,7 +79,7 @@ function getArrayValueSize(e: HDLExpr) : number { } else if (isBinop(e) && e.op == 'arraysel') { return getArrayValueSize(e.left); } else if (isBinop(e) && e.op == 'wordsel') { - return 4; // TODO? for wordsel + return getArrayValueSize(e.left); } throw new HDLError(e, `cannot figure out array value size`); } @@ -91,7 +92,9 @@ function getAlignmentForSize(size) { } function getBinaryenType(size: number) { - return size <= 4 || size > 8 ? binaryen.i32 : binaryen.i64 + if (size <= 4) return binaryen.i32; + else if (size <= 8) return binaryen.i64; + else return binaryen.none; } interface StructRec { @@ -480,7 +483,7 @@ export class HDLModuleWASM implements HDLModuleRunner { if (isArrayItem(e) && isConstExpr(e.expr)) { arr[e.index] = e.expr.cvalue; } else { - throw new HDLError(e, `non-const expr in initarray`); + throw new HDLError(e, `non-const expr in initarray (multidimensional arrays not supported)`); } } //console.log(rec.name, rec.type, arr); @@ -509,8 +512,8 @@ export class HDLModuleWASM implements HDLModuleRunner { var n = 0; return { builtins: { - $finish: (o) => { console.log('... Finished @', o); this.finished = true; }, - $stop: (o) => { console.log('... Stopped @', o); this.stopped = true; }, + $finish: (o) => { if (!this.finished) console.log('... Finished @', o); this.finished = true; }, + $stop: (o) => { if (!this.stopped) console.log('... Stopped @', o); this.stopped = true; }, $time: (o) => BigInt(new Date().getTime()), // TODO: timescale $rand: (o) => (Math.random() * (65536 * 65536)) | 0, $readmem: (o,a,b) => this.$readmem(a, b) @@ -536,6 +539,12 @@ export class HDLModuleWASM implements HDLModuleRunner { return 0; } + // create a new unique label + labelseq = 0; + private label(s?: string) : string { + return `@${s||"label"}_${++this.labelseq}`; + } + private addCopyTraceRecFunction() { const m = this.bmod; const o_TRACERECLEN = this.globals.lookup(TRACERECLEN).offset; @@ -544,11 +553,13 @@ export class HDLModuleWASM implements HDLModuleRunner { const o_TRACEBUF = this.globals.lookup(TRACEBUF).offset; var i32 = binaryen.i32; var none = binaryen.none; + var l_block = this.label("@block"); + var l_loop = this.label("@loop"); m.addFunction("copyTraceRec", binaryen.createType([]), none, [i32, i32, i32], // src, len, dest - m.block("@block", [ + m.block(l_block, [ // $0 = 0 (start of globals) m.local.set(0, m.i32.const(GLOBALOFS)), // don't use $0 as data seg offset, assume trace buffer offsets start @ 0 @@ -557,12 +568,12 @@ export class HDLModuleWASM implements HDLModuleRunner { // $2 = TRACEOFS m.local.set(2, m.i32.load(0, 4, m.i32.const(o_TRACEOFS))), // while ($1--) [$0]++ = [$2]++ - m.loop("@loop", m.block(null, [ + m.loop(l_loop, m.block(null, [ m.i64.store(0, 8, m.local.get(2, i32), m.i64.load(0, 8, m.local.get(0, i32))), m.local.set(0, m.i32.add(m.local.get(0, i32), m.i32.const(8))), m.local.set(2, m.i32.add(m.local.get(2, i32), m.i32.const(8))), m.local.set(1, m.i32.sub(m.local.get(1, i32), m.i32.const(8))), - this.bmod.br_if("@loop", m.local.get(1, i32)) + this.bmod.br_if(l_loop, m.local.get(1, i32)) ])), // TRACEOFS += TRACERECLEN m.i32.store(0, 4, m.i32.const(o_TRACEOFS), @@ -572,7 +583,7 @@ export class HDLModuleWASM implements HDLModuleRunner { ) ), // break if TRACEOFS < TRACEEND - m.br_if("@block", m.i32.lt_u( + m.br_if(l_block, m.i32.lt_u( m.i32.load(0, 4, m.i32.const(o_TRACEOFS)), m.i32.load(0, 4, m.i32.const(o_TRACEEND)) )), @@ -584,6 +595,7 @@ export class HDLModuleWASM implements HDLModuleRunner { private addTick2Function() { const m = this.bmod; + var l_loop = this.label("@loop"); if (this.globals.lookup('clk')) { var l_dseg = m.local.get(0, binaryen.i32); var l_count = m.local.get(1, binaryen.i32); @@ -591,7 +603,7 @@ export class HDLModuleWASM implements HDLModuleRunner { binaryen.createType([binaryen.i32, binaryen.i32]), binaryen.none, [], - m.loop("@loop", m.block(null, [ + m.loop(l_loop, m.block(null, [ this.makeSetVariableFunction("clk", 0), m.drop(m.call("eval", [l_dseg], binaryen.i32)), this.makeSetVariableFunction("clk", 1), @@ -601,7 +613,7 @@ export class HDLModuleWASM implements HDLModuleRunner { // dec $1 m.local.set(1, m.i32.sub(l_count, m.i32.const(1))), // goto @loop if $1 - m.br_if("@loop", l_count) + m.br_if(l_loop, l_count) ])) ); m.addFunctionExport("tick2", "tick2"); @@ -669,7 +681,7 @@ export class HDLModuleWASM implements HDLModuleRunner { var type = getBinaryenType(size); if (type == binaryen.i32) return this.bmod.i32; else if (type == binaryen.i64) return this.bmod.i64; - else throw new HDLError(null, `unknown type for i3264 ${type}`); + else throw new HDLError(dt, `data types > 64 bits not supported`); } private i3264rel(e: HDLBinop) { @@ -726,7 +738,7 @@ export class HDLModuleWASM implements HDLModuleRunner { funccall2wasm(e: HDLFuncCall, opts?:Options) : number { var args = [this.dataptr()]; for (var arg of e.args) { - args.push(this.e2w(arg)); + args.push(this.e2w(arg, {funcarg:true})); } var internal = e.funcname; if (e.funcname.startsWith('$')) { @@ -764,10 +776,10 @@ export class HDLModuleWASM implements HDLModuleRunner { if (local != null) { return this.bmod.local.get(local.index, local.itype); } else if (global != null) { - if (global.size <= 8) - return this.loadmem(this.dataptr(), global.offset, global.size); + if (global.size > 8 && opts && opts.funcarg) + return this.address2wasm(e); // TODO: only applies to wordsel else - return this.address2wasm(e); + return this.loadmem(e, this.dataptr(), global.offset, global.size); } throw new HDLError(e, `cannot lookup variable ${e.refname}`) } @@ -786,18 +798,17 @@ export class HDLModuleWASM implements HDLModuleRunner { if (local != null) { return this.bmod.local.set(local.index, value); } else if (global != null) { - return this.storemem(this.dataptr(), global.offset, global.size, value); + return this.storemem(dest, this.dataptr(), global.offset, global.size, value); } } else if (isBinop(dest)) { - // TODO: array bounds var addr = this.address2wasm(dest); - var elsize = getArrayElementSizeFromExpr(dest.left); - return this.storemem(addr, 0, elsize, value); + var elsize = dest.op == 'wordsel' ? getDataTypeSize(dest.dtype) : getArrayElementSizeFromExpr(dest.left); + return this.storemem(dest, addr, 0, elsize, value); } - throw new HDLError([dest, src], `cannot complete assignment`); + throw new HDLError(dest, `cannot complete assignment`); } - loadmem(ptr, offset:number, size:number) : number { + loadmem(e: HDLSourceObject, ptr, offset:number, size:number) : number { if (size == 1) { return this.bmod.i32.load8_u(offset, 1, ptr); } else if (size == 2) { @@ -807,11 +818,11 @@ export class HDLModuleWASM implements HDLModuleRunner { } else if (size == 8) { return this.bmod.i64.load(offset, 8, ptr); } else { - throw new HDLError(null, `bad size ${size}`) + throw new HDLError(e, `cannot load ${size} bytes (> 64 bits not supported)`) } } - storemem(ptr, offset:number, size:number, value) : number { + storemem(e: HDLSourceObject, ptr, offset:number, size:number, value) : number { if (size == 1) { return this.bmod.i32.store8(offset, 1, ptr, value); } else if (size == 2) { @@ -821,14 +832,14 @@ export class HDLModuleWASM implements HDLModuleRunner { } else if (size == 8) { return this.bmod.i64.store(offset, 8, ptr, value); } else { - throw new HDLError(null, `bad size ${size}`) + throw new HDLError(e, `cannot store ${size} bytes (> 64 bits not supported)`) } } address2wasm(e: HDLExpr) : number { if (isBinop(e) && (e.op == 'arraysel' || e.op == 'wordsel')) { + var elsize = e.op == 'wordsel' ? getDataTypeSize(e.dtype) : getArrayElementSizeFromExpr(e.left); var array = this.address2wasm(e.left); - var elsize = getArrayElementSizeFromExpr(e.left); var index = this.e2w(e.right); return this.bmod.i32.add( array, @@ -850,7 +861,7 @@ export class HDLModuleWASM implements HDLModuleRunner { _arraysel2wasm(e: HDLBinop, opts:Options) : number { var addr = this.address2wasm(e); var elsize = getArrayValueSize(e); - return this.loadmem(addr, 0, elsize); + return this.loadmem(e, addr, 0, elsize); } _wordsel2wasm(e: HDLBinop, opts:Options) : number { @@ -884,15 +895,18 @@ export class HDLModuleWASM implements HDLModuleRunner { } _while2wasm(e: HDLWhileOp, opts:Options) { + var l_block = this.label("@block"); + var l_loop = this.label("@loop"); var block = []; if (e.precond) { block.push(this.e2w(e.precond)); } if (e.loopcond) { + // TODO: detect constant while loop condition block.push(this.bmod.if( this.e2w(e.loopcond, {resulttype:binaryen.i32}), this.bmod.nop(), - this.bmod.br("@block") // exit loop + this.bmod.br(l_block) // exit loop )); } if (e.body) { @@ -901,8 +915,8 @@ export class HDLModuleWASM implements HDLModuleRunner { if (e.inc) { block.push(this.e2w(e.inc)); } - block.push(this.bmod.br("@loop")); - return this.bmod.loop("@loop", this.bmod.block("@block", block, binaryen.none)); + block.push(this.bmod.br(l_loop)); + return this.bmod.loop(l_loop, this.bmod.block(l_block, block, binaryen.none)); } _ccast2wasm(e: HDLUnop, opts:Options) { @@ -953,13 +967,13 @@ export class HDLModuleWASM implements HDLModuleRunner { if (!req) throw new HDLError(e, `no changedet local`); var left = this.e2w(e.left); var right = this.e2w(e.right); + let datainst = this.i3264(hasDataType(e.left) && e.left.dtype); return this.bmod.block(null, [ - // $$req |= (${this.expr2js(e.left)} ^ ${this.expr2js(e.right)}) - this.bmod.local.set(req.index, - this.bmod.i32.or( - this.bmod.local.get(req.index, req.itype), - this.bmod.i32.xor(left, right) // TODO: i64? - ) + // if (left != right) req = 1; + this.bmod.if( + datainst.ne(left, right), + this.bmod.local.set(req.index, this.bmod.i32.const(1)), + this.bmod.nop(), ), // ${this.expr2js(e.right)} = ${this.expr2js(e.left)}` this.assign2wasm(e.right, e.left) diff --git a/src/common/hdl/vxmlparser.ts b/src/common/hdl/vxmlparser.ts index 6254c28c..de4f90a3 100644 --- a/src/common/hdl/vxmlparser.ts +++ b/src/common/hdl/vxmlparser.ts @@ -1,6 +1,6 @@ import { HDLError } from "./hdlruntime"; -import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFile, HDLFuncCall, HDLHierarchyDef, HDLInstanceDef, HDLLogicType, HDLModuleDef, HDLNativeType, HDLPort, HDLSensItem, HDLSourceLocation, HDLTriop, HDLUnit, HDLUnop, HDLUnpackArray, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayType, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef } from "./hdltypes"; +import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataType, HDLDataTypeObject, HDLExpr, HDLExtendop, HDLFile, HDLFuncCall, HDLHierarchyDef, HDLInstanceDef, HDLLogicType, HDLModuleDef, HDLNativeType, HDLPort, HDLSensItem, HDLSourceLocation, HDLSourceObject, HDLTriop, HDLUnit, HDLUnop, HDLUnpackArray, HDLValue, HDLVariableDef, HDLVarRef, HDLWhileOp, isArrayType, isBinop, isBlock, isConstExpr, isFuncCall, isLogicType, isTriop, isUnop, isVarDecl, isVarRef } from "./hdltypes"; /** * Whaa? @@ -17,10 +17,11 @@ import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataT * https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/SharedArrayBuffer */ - export class CompileError extends Error { - constructor(obj: HDLSourceLocation|XMLNode, msg: string) { + export class CompileError extends Error implements HDLSourceObject { + $loc: HDLSourceLocation; + constructor($loc: HDLSourceLocation, msg: string) { super(msg); - console.log(obj); + this.$loc = $loc; Object.setPrototypeOf(this, CompileError.prototype); } } @@ -56,7 +57,7 @@ function parseXMLPoorly(s: string, openfn?: XMLVisitFunction, closefn?: XMLVisit function closetop() { top = stack.pop(); - if (top == null || top.type != ident) throw new CompileError(node, "mismatch close tag: " + ident); + if (top == null || top.type != ident) throw new CompileError(null, "mismatch close tag: " + ident); if (closefn) { top.obj = closefn(top); } @@ -108,6 +109,7 @@ export class VerilogXMLParser implements HDLUnit { cur_node : XMLNode; cur_module : HDLModuleDef; + cur_loc : HDLSourceLocation; cur_deferred = []; constructor() { @@ -138,13 +140,13 @@ export class VerilogXMLParser implements HDLUnit { } name2js(s: string) { - if (s == null) throw new CompileError(null, `no name`); + if (s == null) throw new CompileError(this.cur_loc, `no name`); return s.replace(/[^a-z0-9_]/gi, '$'); } findChildren(node: XMLNode, type: string, required: boolean) : XMLNode[] { var arr = node.children.filter((n) => n.type == type); - if (arr.length == 0 && required) throw new CompileError(node, `no child of type ${type}`); + if (arr.length == 0 && required) throw new CompileError(this.cur_loc, `no child of type ${type}`); return arr; } @@ -152,13 +154,16 @@ export class VerilogXMLParser implements HDLUnit { var loc = node.attrs['loc']; if (loc) { var [fileid, line, col, end_line, end_col] = loc.split(','); - return { - file: this.files[fileid], + var $loc = { + hdlfile: this.files[fileid], + path: this.files[fileid].filename, line: parseInt(line), - col: parseInt(col), - end_line: parseInt(line), - end_col: parseInt(col), + start: parseInt(col)-1, + end_line: parseInt(end_line), + end: parseInt(end_col)-1, } + this.cur_loc = $loc; + return $loc; } else { return null; } @@ -173,7 +178,7 @@ export class VerilogXMLParser implements HDLUnit { instances: [], vardefs: {}, } - if (this.cur_module) throw new CompileError(node, `nested modules not supported`); + if (this.cur_module) throw new CompileError(this.cur_loc, `nested modules not supported`); this.cur_module = module; return module; } @@ -184,7 +189,7 @@ export class VerilogXMLParser implements HDLUnit { this.defer(() => { def.dtype = this.dtypes[dtype_id]; if (!def.dtype) { - throw new CompileError(node, `Unknown data type ${dtype_id} for ${node.type}`); + throw new CompileError(this.cur_loc, `Unknown data type ${dtype_id} for ${node.type}`); } }) } @@ -200,19 +205,19 @@ export class VerilogXMLParser implements HDLUnit { else return BigInt('0x' + numstr); } else { - throw new CompileError(null, `could not parse constant "${s}"`); + throw new CompileError(this.cur_loc, `could not parse constant "${s}"`); } } resolveVar(s: string, mod: HDLModuleDef) : HDLVariableDef { var def = mod.vardefs[s]; - if (def == null) throw new CompileError(null, `could not resolve variable "${s}"`); + if (def == null) throw new CompileError(this.cur_loc, `could not resolve variable "${s}"`); return def; } resolveModule(s: string) : HDLModuleDef { var mod = this.modules[s]; - if (mod == null) throw new CompileError(null, `could not resolve module "${s}"`); + if (mod == null) throw new CompileError(this.cur_loc, `could not resolve module "${s}"`); return mod; } @@ -372,6 +377,14 @@ export class VerilogXMLParser implements HDLUnit { return instance; } + visit_iface(node: XMLNode) { + throw new CompileError(this.cur_loc, `interfaces not supported`); + } + + visit_intfref(node: XMLNode) { + throw new CompileError(this.cur_loc, `interfaces not supported`); + } + visit_port(node: XMLNode) : HDLPort { this.expectChildren(node, 1, 1); var varref: HDLPort = { @@ -435,6 +448,8 @@ export class VerilogXMLParser implements HDLUnit { parent: null, children: node.children.map((n) => n.obj), } + if (node.children.length > 0) + throw new CompileError(this.cur_loc, `multiple non-flattened modules not yet supported`); node.children.forEach((n) => (n.obj as HDLHierarchyDef).parent = hier); this.defer(() => { hier.module = this.resolveModule(node.attrs['submodname']); @@ -467,18 +482,31 @@ export class VerilogXMLParser implements HDLUnit { default: dtype = this.dtypes[dtypename]; if (dtype == null) { - throw new CompileError(node, `unknown data type ${dtypename}`); + throw new CompileError(this.cur_loc, `unknown data type ${dtypename}`); } } this.dtypes[id] = dtype; return dtype; } + visit_refdtype(node: XMLNode) { + } + + visit_enumdtype(node: XMLNode) { + } + + visit_enumitem(node: XMLNode) { + } + visit_packarraydtype(node: XMLNode): HDLDataType { // TODO: packed? return this.visit_unpackarraydtype(node); } + visit_memberdtype(node: XMLNode) { + throw new CompileError(null, `structs not supported`); + } + visit_unpackarraydtype(node: XMLNode): HDLDataType { let id = node.attrs['id']; let sub_dtype_id = node.attrs['sub_dtype_id']; @@ -493,18 +521,18 @@ export class VerilogXMLParser implements HDLUnit { this.dtypes[id] = dtype; this.defer(() => { dtype.subtype = this.dtypes[sub_dtype_id]; - if (!dtype.subtype) throw new CompileError(node, `Unknown data type ${sub_dtype_id} for array`); + if (!dtype.subtype) throw new CompileError(this.cur_loc, `Unknown data type ${sub_dtype_id} for array`); }) return dtype; } else { - throw new CompileError(node, `could not parse constant exprs in array`) + throw new CompileError(this.cur_loc, `could not parse constant exprs in array`) } } visit_senitem(node: XMLNode) : HDLSensItem { var edgeType = node.attrs['edgeType']; if (edgeType != "POS" && edgeType != "NEG") - throw new CompileError(node, "POS/NEG required") + throw new CompileError(this.cur_loc, "POS/NEG required") return { $loc: this.parseSourceLocation(node), edgeType: edgeType, @@ -532,7 +560,7 @@ export class VerilogXMLParser implements HDLUnit { expectChildren(node: XMLNode, low: number, high: number) { if (node.children.length < low || node.children.length > high) - throw new CompileError(node, `expected between ${low} and ${high} children`); + throw new CompileError(this.cur_loc, `expected between ${low} and ${high} children`); } __visit_unop(node: XMLNode) : HDLUnop { @@ -551,7 +579,7 @@ export class VerilogXMLParser implements HDLUnit { var unop = this.__visit_unop(node) as HDLExtendop; unop.width = parseInt(node.attrs['width']); unop.widthminv = parseInt(node.attrs['widthminv']); - if (unop.width != 32) throw new CompileError(node, `extends width ${unop.width} != 32`) + if (unop.width != 32) throw new CompileError(this.cur_loc, `extends width ${unop.width} != 32`) return unop; } @@ -692,6 +720,7 @@ export class VerilogXMLParser implements HDLUnit { visit_display(node: XMLNode) { return null; } visit_sformatf(node: XMLNode) { return null; } + visit_scopename(node: XMLNode) { return null; } visit_readmem(node: XMLNode) { return this.__visit_func(node); } @@ -711,7 +740,7 @@ export class VerilogXMLParser implements HDLUnit { if (method) { return method.bind(this)(node); } else { - throw new CompileError(node, `no visitor for ${node.type}`) + throw new CompileError(this.cur_loc, `no visitor for ${node.type}`) } } diff --git a/src/platform/verilog.ts b/src/platform/verilog.ts index c200109f..4a594149 100644 --- a/src/platform/verilog.ts +++ b/src/platform/verilog.ts @@ -47,6 +47,10 @@ var VERILOG_PRESETS = [ {id:'cpu_platform.v', name:'CPU Platform'}, {id:'test2.asm', name:'16-bit ASM Game'}, {id:'cpu6502.v', name:'6502 CPU'}, + {id:'test_pattern.ice', name:'Test Pattern (Silice)'}, + {id:'copperbars.ice', name:'Animated Bars (Silice)'}, + {id:'rototexture.ice', name:'Rotating Texture (Silice)'}, + //{id:'life.ice', name:'Conway\'s Life (Silice)'}, ]; var VERILOG_KEYCODE_MAP = makeKeycodeMap([ @@ -397,8 +401,8 @@ var VerilogPlatform = function(mainElement, options) { } else if (!framehsync && top.state.hsync) { framehsync = true; } else if ((framehsync && !top.state.hsync) || framex > videoWidth*2) { + if (sync && framehsync) scanlineCycles = framex; // set cycles/scanline for fast update function framehsync = false; - if (sync) scanlineCycles = framex; framex = 0; framey++; top.state.hpaddle = framey > video.paddle_x ? 1 : 0; @@ -425,7 +429,7 @@ var VerilogPlatform = function(mainElement, options) { // use trace buffer to update video updateVideoFrameFast(tmod: HDLModuleTrace) { var maxLineCycles = 1009; // prime number so we eventually sync up - var nextlineCycles = scanlineCycles; + var nextlineCycles = scanlineCycles || maxLineCycles; // TODO: we can go faster if no paddle/sound frameidx = 0; var wasvsync = false; @@ -460,19 +464,21 @@ var VerilogPlatform = function(mainElement, options) { if (tmod.trace.hsync) { if (!hsyncStart) hsyncStart = n; hsyncEnd = n; - } else if (hsyncEnd) + } else if (hsyncEnd) { break; + } spkr(); tmod.nextTrace(); n++; } // see if our scanline cycle count is stable (can't read tmod.trace after end of line) - if (hsyncStart < hsyncEnd && hsyncEnd == scanlineCycles-1) { + if (hsyncStart < hsyncEnd && hsyncEnd == nextlineCycles-1) { // scanline cycle count locked in, reset buffer to improve cache locality - nextlineCycles = scanlineCycles; tmod.resetTrace(); + nextlineCycles = scanlineCycles; } else { - // not in sync, don't reset buffer (TODO: take some of the cycles back) + // not in sync, don't reset buffer + // TODO: determine scanlineCycles here instead of letting slow loop do it //console.log('scanline', framey, scanlineCycles, nextlineCycles, n, hsyncStart, hsyncEnd); nextlineCycles = Math.min(maxLineCycles, n + scanlineCycles); } @@ -676,6 +682,7 @@ var VerilogPlatform = function(mainElement, options) { getFrameRate() { return frameRate; } poweron() { + if (!top) return; top.powercycle(); this.reset(); } @@ -690,6 +697,7 @@ var VerilogPlatform = function(mainElement, options) { if (!this.hasvideo) this.resume(); // TODO? } tick() { + if (!top) return; top.tick2(1); } getToolForFilename(fn) { @@ -706,7 +714,7 @@ var VerilogPlatform = function(mainElement, options) { inspect_obj = inspect_sym = null; return; } - var val = top.state[name]; + var val = top && top.state[name]; /* TODO if (val === undefined && current_output.code) { var re = new RegExp("(\\w+__DOT__(?:_[dcw]_)" + name + ")\\b", "gm"); @@ -730,17 +738,17 @@ var VerilogPlatform = function(mainElement, options) { getDebugTree() { return { runtime: top, - state: top.getGlobals() + state: top && top.getGlobals() } } // TODO: bind() a function to avoid depot? saveState() { - return {o: top.saveState()}; + return {o: top && top.saveState()}; } loadState(state) { - top.loadState(state.o); + if (state.o) top.loadState(state.o); } saveControlsState() { diff --git a/src/worker/workermain.ts b/src/worker/workermain.ts index 23418ada..72547967 100644 --- a/src/worker/workermain.ts +++ b/src/worker/workermain.ts @@ -1,6 +1,6 @@ "use strict"; -import { WorkerResult, WorkerFileUpdate, WorkerBuildStep, WorkerMessage, WorkerError, Dependency, SourceLine, CodeListing, CodeListingMap, Segment, WorkerOutput } from "../common/workertypes"; +import { WorkerResult, WorkerFileUpdate, WorkerBuildStep, WorkerMessage, WorkerError, Dependency, SourceLine, CodeListing, CodeListingMap, Segment, WorkerOutput, SourceLocation } from "../common/workertypes"; declare var WebAssembly; declare function importScripts(path:string); @@ -20,8 +20,8 @@ var wasmMemory; function getWASMMemory() { if (wasmMemory == null) { wasmMemory = new WebAssembly.Memory({ - 'initial': 32768, - 'maximum': 32768, + 'initial': 1024, // 64MB + 'maximum': 16384, // 1024MB }); } return wasmMemory; @@ -1661,7 +1661,7 @@ function preprocessMCPP(step:BuildStep, filesys:string) { function detectModuleName(code:string) { var m = /^\s*module\s+(\w+_top)\b/m.exec(code) - || /^\s*module\s+(top)\b/m.exec(code) + || /^\s*module\s+(top|t)\b/m.exec(code) || /^\s*module\s+(\w+)\b/m.exec(code); return m ? m[1] : null; } @@ -1772,8 +1772,8 @@ function compileVerilator(step:BuildStep) { loadRequire("hdltypes", "common/hdl/hdltypes"); loadRequire("vxmlparser", "common/hdl/vxmlparser"); var platform = step.platform || 'verilog'; - var errors = []; - var asmlines = []; + var errors : WorkerError[] = []; + var asmlines : SourceLine[] = []; gatherFiles(step); // compile verilog if files are stale var xmlPath = "main.xml"; @@ -1803,7 +1803,7 @@ function compileVerilator(step:BuildStep) { try { var args = ["--cc", "-O3"/*abcdefstzsuka*/, "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod, "-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat', - "--x-assign", "fast", "--noassert", "--pins-bv", "33", + "--x-assign", "fast", "--noassert", "--pins-sc-biguint", "--xml-output", xmlPath, "--top-module", topmod, step.path] verilator_mod.callMain(args); @@ -1829,7 +1829,12 @@ function compileVerilator(step:BuildStep) { xmlParser.parse(xmlContent); } catch(e) { console.log(e, e.stack); - errors.push({line:0,msg:""+e}); + if (e.$loc != null) { + let $loc = e.$loc as SourceLocation; + errors.push({msg:""+e, path:$loc.path, line:$loc.line}); + } else { + errors.push({line:0,msg:""+e}); + } return {errors:errors, listings:listings}; } //rtn.intermediate = {listing:h_file + cpp_file}; // TODO diff --git a/test/cli/testverilog.js b/test/cli/testverilog.js index 1b8f711d..4641bf52 100644 --- a/test/cli/testverilog.js +++ b/test/cli/testverilog.js @@ -6,6 +6,10 @@ var _cproc = require('child_process'); var fs = require('fs'); var wtu = require('./workertestutils.js'); var heapdump = require("heapdump"); +var commandExists = require('command-exists'); + +var has_yosys = commandExists('yosys'); +var has_iverilog = commandExists('iverilog'); createTestDOM(); @@ -71,7 +75,7 @@ function compileVerilator(filename, code, callback, nerrors, depends) { global.postMessage = async function(msg) { try { if (msg.errors && msg.errors.length) { - console.log(msg.errors); + if (msg.errors.length > 0 && nerrors == 0) throw new Error(JSON.stringify(msg.errors)); assert.equal(nerrors||0, msg.errors.length, "errors"); } else { assert.equal(nerrors||0, 0, "errors"); @@ -84,12 +88,8 @@ function compileVerilator(filename, code, callback, nerrors, depends) { } callback(null, msg); } catch (e) { - if (e.msg && e.msg.indexOf('WebAssembly.Memory()') >= 0) { - process.exit(1); - } else { - //fs.unlinkSync(filename); - callback(e, null); - } + console.log('rm', filename); //fs.unlinkSync(filename); + callback(e, null); } }; // send files to worker for build @@ -101,23 +101,38 @@ function compileVerilator(filename, code, callback, nerrors, depends) { } }); } catch (e) { - if (e.msg && e.msg.indexOf('WebAssembly.Memory()') >= 0) { - process.exit(1); - } else { - //fs.unlinkSync(filename); - callback(e, null); - } + console.log('rm', filename); //fs.unlinkSync(filename); + callback(e, null); } } function testIcarus(filename) { - _cproc.execSync('iverilog -I./presets/verilog ./' + filename); + if (has_iverilog) it('should icarus '+filename, function(done) { + _cproc.exec('iverilog -g2012 -I./presets/verilog -I./tests/cli/verilog ./' + filename, function(err,stdout,stderr) { + if (err) { + console.log(stdout); + console.log(stderr); + } + done(err); + }); + }); +} + +function testYosys(filename) { + if (has_yosys) it('should yosys '+filename, function(done) { + _cproc.exec(`yosys -q -p "read_verilog -sv ./${filename}"`, function(err,stdout,stderr) { + if (err) { + console.log(stdout); + console.log(stderr); + } + done(err); + }); + }); } function testVerilator(filename, disables, nerrors, depends) { - it('should translate '+filename, function(done) { + it('should verilate '+filename, function(done) { console.log(filename); - //if (depends) testIcarus(filename); var csource = ab2str(fs.readFileSync(filename)); var header = ''; for (var i=0; i<(disables||[]).length; i++) @@ -126,29 +141,43 @@ function testVerilator(filename, disables, nerrors, depends) { }); } +function testModule(filename, disables, nerrors, depends) { + testVerilator(filename, disables, nerrors, depends); + //testIcarus(filename); + //testYosys(filename); +} + describe('Verilog Worker', function() { var files = _fs.readdirSync('test/cli/verilog').filter(fn => fn.endsWith('.v')); //files = files.slice(0,75); for (var fn of files) { - testVerilator('test/cli/verilog/' + fn, + testModule('test/cli/verilog/' + fn, ['UNDRIVEN','BLKSEQ','WIDTH','PINCONNECTEMPTY','SYNCASYNCNET','UNOPT','UNOPTFLAT','VARHIDDEN','EOFNEWLINE','ASSIGNDLY','CASEX','SYMRSVDWORD','STMTDLY','PROCASSWIRE'] ); global.onmessage({data:{reset:true}}); } - testVerilator('presets/verilog/hvsync_generator.v'); - testVerilator('presets/verilog/digits10.v', null, null, ['digits10.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/scoreboard.v', null, null, ['scoreboard.v', 'digits10.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/ball_paddle.v', null, null, ['ball_paddle.v', 'scoreboard.v', 'digits10.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/sprite_rotation.v', null, null, ['sprite_rotation.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/lfsr.v'); - testVerilator('presets/verilog/starfield.v', null, null, ['starfield.v', 'lfsr.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/ram.v'); - testVerilator('presets/verilog/font_cp437_8x8.v'); - testVerilator('presets/verilog/sprite_scanline_renderer.v', null, null, ['sprite_scanline_renderer.v', 'ram.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']); - testVerilator('presets/verilog/cpu6502.v'); + testModule('presets/verilog/hvsync_generator.v'); + testModule('presets/verilog/test_hvsync.v', null, null, ['test_hvsync.v', 'hvsync_generator.v']); + testModule('presets/verilog/digits10.v', null, null, ['digits10.v', 'hvsync_generator.v']); + testModule('presets/verilog/scoreboard.v', null, null, ['scoreboard.v', 'digits10.v', 'hvsync_generator.v']); + testModule('presets/verilog/ball_paddle.v', null, null, ['ball_paddle.v', 'scoreboard.v', 'digits10.v', 'hvsync_generator.v']); + testModule('presets/verilog/sprite_rotation.v', null, null, ['sprite_rotation.v', 'hvsync_generator.v']); + testModule('presets/verilog/lfsr.v'); + testModule('presets/verilog/starfield.v', null, null, ['starfield.v', 'lfsr.v', 'hvsync_generator.v']); + testModule('presets/verilog/ram.v'); + testModule('presets/verilog/font_cp437_8x8.v'); + testModule('presets/verilog/sprite_scanline_renderer.v', null, null, ['sprite_scanline_renderer.v', 'ram.v', 'hvsync_generator.v']); + testModule('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']); + testModule('presets/verilog/cpu6502.v'); + + testYosys('presets/verilog/ball_paddle.v'); + testYosys('presets/verilog/starfield.v'); + testYosys('presets/verilog/racing_game.v'); + testYosys('presets/verilog/racing_game_cpu.v'); + // TODO: fix testYosys('presets/verilog/cpu_platform.v'); + testYosys('presets/verilog/cpu6502.v'); }).afterAll(() => { /* diff --git a/test/cli/verilog/t_EXAMPLE.v b/test/cli/verilog/t_EXAMPLE.v new file mode 100644 index 00000000..032785ac --- /dev/null +++ b/test/cli/verilog/t_EXAMPLE.v @@ -0,0 +1,97 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by ____YOUR_NAME_HERE____. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test(/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input clk; + input [31:0] in; + output reg [31:0] out; + + always @(posedge clk) begin + out <= in; + end +endmodule diff --git a/test/cli/verilog/t_dynarray_param.v b/test/cli/verilog/t_dynarray_param.v deleted file mode 100644 index 72098b87..00000000 --- a/test/cli/verilog/t_dynarray_param.v +++ /dev/null @@ -1,54 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Noam Gallmann. -// SPDX-License-Identifier: CC0-1.0 - -`define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) - -module t(/*AUTOARG*/); - localparam int SIZES [3:0] = '{1,2,3,4}; - typedef int calc_sums_t [3:0]; - - localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4); - function calc_sums_t calc_sums_array(int s[3:0], int n); - int sum = 0; - for (int ii = 0; ii < n; ++ii) begin - sum = sum + s[ii]; - calc_sums_array[ii] = sum; - end - endfunction - -`ifndef VERILATOR - localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4); -`endif - function calc_sums_t calc_sums_dyn(int s[], int n); - int sum = 0; - for (int ii = 0; ii < n; ++ii) begin - sum = sum + s[ii]; - calc_sums_dyn[ii] = sum; - end - endfunction - - initial begin - `checkh(SIZES[0], 4); - `checkh(SIZES[1], 3); - `checkh(SIZES[2], 2); - `checkh(SIZES[3], 1); - - `checkh(SUMS_ARRAY[0], 4); - `checkh(SUMS_ARRAY[1], 7); - `checkh(SUMS_ARRAY[2], 9); - `checkh(SUMS_ARRAY[3], 10); - -`ifndef VERILATOR - `checkh(SUMS_DYN[0], 1); - `checkh(SUMS_DYN[1], 3); - `checkh(SUMS_DYN[2], 6); - `checkh(SUMS_DYN[3], 10); -`endif - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test/cli/verilog/t_gate_elim.v b/test/cli/verilog/t_gate_elim.v new file mode 100644 index 00000000..910a0ff4 --- /dev/null +++ b/test/cli/verilog/t_gate_elim.v @@ -0,0 +1,122 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg b; + + wire vconst1 = 1'b0; + wire vconst2 = !(vconst1); + wire vconst3 = !vconst2; + wire vconst = vconst3; + + wire qa; + wire qb; + wire qc; + wire qd; + wire qe; + ta ta (.b(b), .vconst(vconst), .q(qa)); + tb tb (.clk(clk), .vconst(vconst), .q(qb)); + tc tc (.b(b), .vconst(vconst), .q(qc)); + td td (.b(b), .vconst(vconst), .q(qd)); + te te (.clk(clk), .b(b), .vconst(vconst), .q(qe)); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $display("%b",{qa,qb,qc,qd,qe}); +`endif + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + b <= 1'b1; + end + if (cyc==2) begin + if (qa!=1'b1) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + b <= 1'b0; + end + if (cyc==3) begin + if (qa!=1'b0) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + if (qe!=1'b0) $stop; + b <= 1'b1; + end + if (cyc==4) begin + if (qa!=1'b1) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + if (qe!=1'b1) $stop; + b <= 1'b0; + end + if (cyc==5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module ta ( + input vconst, + input b, + output reg q); + + always @ (/*AS*/b or vconst) begin + q = vconst | b; + end +endmodule + +module tb ( + input vconst, + input clk, + output reg q); + + always @ (posedge clk) begin + q <= vconst; + end +endmodule + +module tc ( + input vconst, + input b, + output reg q); + always @ (posedge vconst) begin + q <= b; + $stop; + end +endmodule + +module td ( + input vconst, + input b, + output reg q); + + always @ (/*AS*/vconst) begin + q = vconst; + end +endmodule + +module te ( + input clk, + input vconst, + input b, + output reg q); + reg qmid; + always @ (posedge vconst or posedge clk) begin + qmid <= b; + end + always @ (posedge clk or posedge vconst) begin + q <= qmid; + end +endmodule diff --git a/test/cli/verilog/t_gate_lvalue_const.v b/test/cli/verilog/t_gate_lvalue_const.v new file mode 100644 index 00000000..ac003d8f --- /dev/null +++ b/test/cli/verilog/t_gate_lvalue_const.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk, rst + ); + + input clk; + input rst; + + logic [2:0] ctrl_inc_single; + logic [2:0] ctrl_inc_double; + + logic [2:0] cnt_single; + always_ff @(posedge clk) begin + if (rst) begin + cnt_single <= '0; + end + else if (ctrl_inc_single != '0 && cnt_single != '1) begin + cnt_single <= cnt_single + 1'd1; + end + end + + logic [2:0] cnt_double; + always_ff @(posedge clk) begin + if (rst) begin + cnt_double <= '0; + end + else if (ctrl_inc_double != '0 && cnt_double != '1) begin + cnt_double <= cnt_double + 1'd1; + end + end + + always_comb ctrl_inc_single = '0; + always_comb ctrl_inc_double = '0; + + testMod test_i (.data_i(cnt_single)); + testMod test_j (.data_i(cnt_double)); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module testMod + (input wire [2:0] data_i); + + typedef logic [63:0] time_t; + time_t [2:0] last_transition; + genvar b; + + generate + for (b = 0; b <= 2; b++) begin : gen_trans + always_ff @(posedge data_i[b] or negedge data_i[b]) begin + last_transition[b] <= $time; + end + end + endgenerate + +endmodule diff --git a/test/cli/verilog/t_gated_clk_1.v b/test/cli/verilog/t_gated_clk_1.v new file mode 100644 index 00000000..65c4a13e --- /dev/null +++ b/test/cli/verilog/t_gated_clk_1.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Test of gated clock detection +// +// The code as shown generates a result by a delayed assignment from PC. The +// creation of the result is from a clock gated from the clock that sets +// PC. Howevever since they are essentially the same clock, the result should +// be delayed by one cycle. +// +// Standard Verilator treats them as different clocks, so the result stays in +// step with the PC. An event drive simulator always allows the clock to win. +// +// The problem is caused by the extra loop added by Verilator to the +// evaluation of all internally generated clocks (effectively removed by +// marking the clock enable). +// +// This test is added to facilitate experiments with solutions. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett . +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg gated_clk_en = 1'b0 ; + reg [1:0] pc = 2'b0; + reg [1:0] res = 2'b0; + + wire gated_clk = gated_clk_en & clk; + + always @(posedge clk) begin + pc <= pc + 1; + gated_clk_en <= 1'b1; + end + + always @(posedge gated_clk) begin + res <= pc; + end + + always @(posedge clk) begin + if (pc == 2'b11) begin + // Correct behaviour is that res should be lagging pc in the count + // by one cycle + if (res == 2'b10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_gen_cond_bitrange.v b/test/cli/verilog/t_gen_cond_bitrange.v new file mode 100644 index 00000000..57b7fd5e --- /dev/null +++ b/test/cli/verilog/t_gen_cond_bitrange.v @@ -0,0 +1,139 @@ +// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if" +// +// The given generate loops should only access valid bits of mask, since that +// is defined by SIZE. However since the loop range is larger, this only works +// if short-circuited evaluation of the generate loop is in place. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +`define MAX_SIZE 4 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (2'b11)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; + + initial begin + count = 0; + end + + always @(posedge clk) begin + if (count == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + count = count + 1; + end + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that rely on short-circuiting of the logic to avoid errors. + generate + genvar g; + + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) || ~MASK[g])) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g < SIZE) -> ~MASK[g])) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ( g < SIZE ? MASK[g] : 1'b0) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + + // The other way round + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ( g >= SIZE ? 1'b0 : MASK[g]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); +`endif + if (g >= SIZE) begin + $stop; + end + end + end + end + endgenerate + +endmodule diff --git a/test/cli/verilog/t_gen_cond_const.v b/test/cli/verilog/t_gen_cond_const.v new file mode 100644 index 00000000..870ee4f1 --- /dev/null +++ b/test/cli/verilog/t_gen_cond_const.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test for generate IF constants +// +// The given generate loop should have a constant expression as argument. This +// test checks it really does evaluate as constant. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + + +`define MAX_SIZE 4 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (4'b1111)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; + + initial begin + count = 0; + end + + always @(posedge clk) begin + if (count == 1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + count = count + 1; + end + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that rely on short-circuiting of the logic to avoid + // errors. + generate + if ((SIZE < 8'h04) && MASK[0]) begin + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write ("Generate IF MASK[0] = %d\n", MASK[0]); +`endif + end + end + endgenerate + +endmodule diff --git a/test/cli/verilog/t_gen_div0.v b/test/cli/verilog/t_gen_div0.v new file mode 100644 index 00000000..d9cc0eb0 --- /dev/null +++ b/test/cli/verilog/t_gen_div0.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOINST*/); + + Test #( + .BIT_WIDTH (72), + .BYTE_WIDTH (9) + ) + + u_test_inst(); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test (); + + parameter BIT_WIDTH = ""; + parameter BYTE_WIDTH = ""; + + localparam BYTES = BIT_WIDTH / BYTE_WIDTH; + + wire [BYTES - 1:0] i; + wire [BYTES - 1:0] o; + + genvar g; + generate + for (g = 0; g < BYTES; g = g + 1) begin: gen + assign o[g] = (i[g] !== 1'b0); + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_gen_for.v b/test/cli/verilog/t_gen_for.v new file mode 100644 index 00000000..4ca2596d --- /dev/null +++ b/test/cli/verilog/t_gen_for.v @@ -0,0 +1,173 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + reg [7:0] crc; + genvar g; + + wire [7:0] out_p1; + wire [15:0] out_p2; + wire [7:0] out_p3; + wire [7:0] out_p4; + + paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); + paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); + paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); + gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); + + wire [7:0] out_ef; + enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==0) begin + // Setup + crc <= 8'hed; + end + else if (cyc==1) begin + end + else if (cyc==3) begin + if (out_p1 !== 8'h2d) $stop; + if (out_p2 !== 16'h2d2d) $stop; + if (out_p3 !== 8'h78) $stop; + if (out_p4 !== 8'h44) $stop; + if (out_ef !== 8'hda) $stop; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module gencase (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter MODE = 0; + input [7:0] in; + output [7:0] out; + generate // : genblk1 + begin + case (MODE) + 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); + default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); + endcase + end + endgenerate + +endmodule + +module paramed (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter WIDTH = 1; + parameter MODE = 0; + input [WIDTH-1:0] in; + output [WIDTH-1:0] out; + + generate + if (MODE==0) initial $write("Mode=0\n"); + // No else + endgenerate + +`ifndef NC // for(genvar) unsupported + `ifndef ATSIM // for(genvar) unsupported + generate + // Empty loop body, local genvar + for (genvar j=0; j<3; j=j+1) begin end + // Ditto to make sure j has new scope + for (genvar j=0; j<5; j=j+1) begin end + endgenerate + `endif +`endif + + generate + endgenerate + + genvar i; + generate + if (MODE==0) begin + // Flip bitorder, direct assign method + for (i=0; i= 0; i = i-1) begin: fnxtclk1 + fnxtclk fnxtclk1 + (.u(c[i]), + .reset(reset), + .clk(clk), + .w(d[i]) ); + end + endgenerate + + assign b = d[0]; + assign c[0] = my_sig; + assign my_sig = 1'b1; + +endmodule + +module fnxtclk (u, reset, clk, w ); + input u; + input reset; + input clk; + output reg w; + + always @ (posedge clk or posedge reset) begin + if (reset == 1'b1) begin + w <= 1'b0; + end + else begin + w <= u; + end + end + +endmodule diff --git a/test/cli/verilog/t_gen_for_interface.v b/test/cli/verilog/t_gen_for_interface.v new file mode 100644 index 00000000..63dff454 --- /dev/null +++ b/test/cli/verilog/t_gen_for_interface.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 + +parameter N = 5; + +interface intf; + logic [N-1:0] data; +endinterface + +module t ( + input logic clk + ); + intf localinterface [N-1:0](); + + generate + genvar i,j; + for(i = 0; i < N; i++) begin + logic [N-1:0] dummy; + for(j = 0; j < N; j++) begin + assign dummy[j] = localinterface[j].data[i]; + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_gen_for_overlap.v b/test/cli/verilog/t_gen_for_overlap.v new file mode 100644 index 00000000..1a0bdcc8 --- /dev/null +++ b/test/cli/verilog/t_gen_for_overlap.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug749 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + genvar g; + for (g=1; g<3; ++g) begin : gblk + sub2 #(.IN(g)) u (); + //sub #(.IN(g)) u2 (); + end + + sub1 #(.IN(0)) u (); + + always @ (posedge clk) begin + if (t.u.IN != 0) $stop; + if (t.u.FLAVOR != 1) $stop; + //if (t.u2.IN != 0) $stop; // This should be not found + if (t.gblk[1].u.IN != 1) $stop; + if (t.gblk[2].u.IN != 2) $stop; + if (t.gblk[1].u.FLAVOR != 2) $stop; + if (t.gblk[2].u.FLAVOR != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub1 (/*AUTOARG*/); + parameter [31:0] IN = 99; + parameter FLAVOR = 1; +`ifdef TEST_VERBOSE + initial $display("%m"); +`endif +endmodule + +module sub2 (/*AUTOARG*/); + parameter [31:0] IN = 99; + parameter FLAVOR = 2; +`ifdef TEST_VERBOSE + initial $display("%m"); +`endif +endmodule diff --git a/test/cli/verilog/t_gen_for_shuffle.v b/test/cli/verilog/t_gen_for_shuffle.v new file mode 100644 index 00000000..b71f4ffa --- /dev/null +++ b/test/cli/verilog/t_gen_for_shuffle.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3e3a62edb61f8c7f + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [31:0] in; + output [31:0] out; + + genvar i; + generate + for (i=0; i<16; i=i+1) begin : gblk + assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_gen_inc.v b/test/cli/verilog/t_gen_inc.v new file mode 100644 index 00000000..e2fbbce2 --- /dev/null +++ b/test/cli/verilog/t_gen_inc.v @@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + genvar g; + integer i; + + reg [31:0] v; + + reg [31:0] gen_pre_PLUSPLUS = 32'h0; + reg [31:0] gen_pre_MINUSMINUS = 32'h0; + reg [31:0] gen_post_PLUSPLUS = 32'h0; + reg [31:0] gen_post_MINUSMINUS = 32'h0; + reg [31:0] gen_PLUSEQ = 32'h0; + reg [31:0] gen_MINUSEQ = 32'h0; + reg [31:0] gen_TIMESEQ = 32'h0; + reg [31:0] gen_DIVEQ = 32'h0; + reg [31:0] gen_MODEQ = 32'h0; + reg [31:0] gen_ANDEQ = 32'h0; + reg [31:0] gen_OREQ = 32'h0; + reg [31:0] gen_XOREQ = 32'h0; + reg [31:0] gen_SLEFTEQ = 32'h0; + reg [31:0] gen_SRIGHTEQ = 32'h0; + reg [31:0] gen_SSRIGHTEQ = 32'h0; + + generate + for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; + for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; + for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; + for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; + for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; + for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; + for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; + for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; + for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; + for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; + for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; + for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; + for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; + endgenerate + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 3) begin +`ifdef TEST_VERBOSE + $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); + $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); + $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); + $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); + $write("gen_PLUSEQ %b\n", gen_PLUSEQ); + $write("gen_MINUSEQ %b\n", gen_MINUSEQ); + $write("gen_TIMESEQ %b\n", gen_TIMESEQ); + $write("gen_DIVEQ %b\n", gen_DIVEQ); + $write("gen_MODEQ %b\n", gen_MODEQ); + $write("gen_ANDEQ %b\n", gen_ANDEQ); + $write("gen_OREQ %b\n", gen_OREQ); + $write("gen_XOREQ %b\n", gen_XOREQ); + $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); + $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); + $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); +`endif + if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; + if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; + if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; + if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; + if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + + v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; + v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; + v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; + v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_gen_index.v b/test/cli/verilog/t_gen_index.v new file mode 100644 index 00000000..810266ad --- /dev/null +++ b/test/cli/verilog/t_gen_index.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Test generate index usage. +// +// The code illustrates a problem in Verilator's handling of constant +// expressions inside generate indexes. +// +// This is a regression test against issue 517. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +`define START 8 +`define SIZE 4 +`define END (`START + `SIZE) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [`END-1:0] y; + wire [`END-1:0] x; + + foo foo_i (.y (y), + .x (x), + .clk (clk)); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule // t + + +module foo(output wire [`END-1:0] y, + input wire [`END-1:0] x, + input wire clk); + + function peek_bar; + peek_bar = bar_inst[`START].i_bar.r; // this is ok + peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not. + endfunction + + genvar g; + generate + for (g = `START; g < `END; g = g + 1) begin: bar_inst + bar i_bar(.x (x[g]), + .y (y[g]), + .clk (clk)); + end + endgenerate + +endmodule : foo + + +module bar(output wire y, + input wire x, + input wire clk); + + reg r = 0; + assign y = r; + + always @(posedge clk) begin + r = x ? ~x : y; + end + +endmodule : bar diff --git a/test/cli/verilog/t_gen_intdot2.v b/test/cli/verilog/t_gen_intdot2.v new file mode 100644 index 00000000..a2f3886c --- /dev/null +++ b/test/cli/verilog/t_gen_intdot2.v @@ -0,0 +1,161 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + reg check; + initial check = 1'b0; + Genit g (.clk(clk), .check(check)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + check <= 1'b0; + end + else if (cyc==1) begin + check <= 1'b1; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +//`define WAVES +`ifdef WAVES + initial begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"}); + $dumpvars(12, t); + end +`endif + +endmodule + +module One; + wire one = 1'b1; +endmodule + +module Genit ( + input clk, + input check); + + // ARRAY + One cellarray1[1:0] (); //cellarray[0..1][0..1] + always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; + always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; + + // IF + generate + // genblk1 refers to the if's name, not the "generate" itself. + if (1'b1) // IMPLIED begin: genblk1 + One ifcell1(); // genblk1.ifcell1 + else + One ifcell1(); // genblk1.ifcell1 + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; + + generate + begin : namedif2 + if (1'b1) + One ifcell2(); // namedif2.genblk1.ifcell2 + end + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop; + + generate + if (1'b1) + begin : namedif3 + One ifcell3(); // namedif3.ifcell3 + end + endgenerate + always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; + + // CASE + generate + begin : casecheck + case (1'b1) + 1'b1 : + One casecell10(); // genblk4.casecell10 + endcase + end + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (casecheck.genblk1.casecell10.one !== 1'b1) $stop; + + generate + case (1'b1) + 1'b1 : begin : namedcase11 + One casecell11(); + end + endcase + endgenerate + always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; + + genvar i; + genvar j; + + generate + begin : genfor + for (i = 0; i < 2; i = i + 1) + One cellfor20 (); // genfor.genblk1[0..1].cellfor20 + end + endgenerate + // DISAGREEMENT on this naming + always @ (posedge clk) if (genfor.genblk1[0].cellfor20.one !== 1'b1) $stop; + always @ (posedge clk) if (genfor.genblk1[1].cellfor20.one !== 1'b1) $stop; + + // COMBO + generate + for (i = 0; i < 2; i = i + 1) + begin : namedfor21 + One cellfor21 (); // namedfor21[0..1].cellfor21 + end + endgenerate + always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; + + generate + for (i = 0; i < 2; i = i + 1) + begin : namedfor30 + for (j = 0; j < 2; j = j + 1) + begin : forb30 + if (j == 0) + begin : forif30 + One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a + end + else +`ifdef verilator + begin : forif30b +`else + begin : forif30 // forif30 seems to work on some simulators, not verilator yet +`endif + One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b + end + end + end + endgenerate + always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; +`ifdef verilator + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; +`else + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; +`endif + +endmodule diff --git a/test/cli/verilog/t_gen_local.v b/test/cli/verilog/t_gen_local.v new file mode 100644 index 00000000..f9adfd46 --- /dev/null +++ b/test/cli/verilog/t_gen_local.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + localparam N = 31; + + wire [31:0] vec; + + generate + genvar g; // bug461 + begin : topgen + for (g=0; g10 && cyc<90) begin + sum <= {sum[1:0],sum[2]} ^ out; + end + else if (cyc==99) begin + if (crc !== 8'b01110000) $stop; + if (sum !== 3'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module dffn (q,d,clk); + parameter BITS = 1; + + input [BITS-1:0] d; + output reg [BITS-1:0] q; + input clk; + + always @ (posedge clk) begin + q <= d; + end + +endmodule + +module MxN_pipeline (in, out, clk); + parameter M=3, N=4; + + input [M-1:0] in; + output [M-1:0] out; + input clk; + + // Unsupported: Per-bit array instantiations with output connections to non-wires. + //wire [M*(N-1):1] t; + //dffn #(M) p[N:1] ({out,t},{t,in},clk); + + wire [M*(N-1):1] w; + wire [M*N:1] q; + dffn #(M) p[N:1] (q,{w,in},clk); + assign {out,w} = q; + +endmodule diff --git a/test/cli/verilog/t_inst_port_array.v b/test/cli/verilog/t_inst_port_array.v new file mode 100644 index 00000000..ef5071f5 --- /dev/null +++ b/test/cli/verilog/t_inst_port_array.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Alex Solomatnikov. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + logic [6-1:0] foo[4-1:0]; + + //initial $display("%m: %p\n", foo); + //initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice + //logic [6-1:0] foo2[4-1:0][5:6]; + //initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal + + dut #(.W(6), + .D(4)) udut(.clk(clk), + .foo(foo[4-1:0])); +endmodule + +module dut + #(parameter W = 1, + parameter D = 1) + (input logic clk, + input logic [W-1:0] foo[D-1:0]); + + genvar i, j; + generate + for (j = 0; j < D; j++) begin + for (i = 0; i < W; i++) begin + suba ua(.clk(clk), .foo(foo[j][i])); + end + end + endgenerate +endmodule + +module suba + (input logic clk, + input logic foo); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_inst_prepost.v b/test/cli/verilog/t_inst_prepost.v new file mode 100644 index 00000000..2d50acb3 --- /dev/null +++ b/test/cli/verilog/t_inst_prepost.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + sub #(10,11,12,13) sub (); + +endmodule + +module sub (); + parameter A = 0; + parameter B = 1; + + ip ip(); + + parameter C = 2; + parameter D = 3; + + initial begin + if (A!=10) $stop; + if (B!=11) $stop; + if (C!=12) $stop; + if (D!=13) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module ip; +endmodule diff --git a/test/cli/verilog/t_inst_signed.v b/test/cli/verilog/t_inst_signed.v new file mode 100644 index 00000000..7529608a --- /dev/null +++ b/test/cli/verilog/t_inst_signed.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + + wire signed [7:0] sgn_wide; + wire [7:0] unsgn_wide; + + // The instantiation will Z extend, not sign extend + // verilator lint_off WIDTH + sub sub (.clk, + .sgn(sgn_wide), .unsgn(unsgn_wide), + .iss(3'sh7), .isu(3'h7), + .ius(3'sh7), .iuu(3'h7)); + // verilator lint_on WIDTH + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide); +`endif + if (sgn_wide[2:0] != 3'sh7) $stop; + if (unsgn_wide[2:0] != 3'h7) $stop; + // Simulators differ here. + if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC + && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS + if (unsgn_wide !== 8'sbzzzzz111 + && unsgn_wide!== 8'sb00000111) $stop; + cyc <= cyc + 1; + if (cyc==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub ( + input clk, + output wire signed [2:0] sgn, + output wire [2:0] unsgn, + input signed [7:0] iss, + input signed [7:0] isu, + input [7:0] ius, + input [7:0] iuu); + assign sgn = 3'sh7; + assign unsgn = 3'h7; + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("in: %x %x %x %x\n", iss, isu, ius, iuu); + if (iss != 8'hff) $stop; + if (isu != 8'h07) $stop; + if (ius != 8'hff) $stop; + if (iuu != 8'h07) $stop; +`endif + end + +endmodule diff --git a/test/cli/verilog/t_inst_signed1.v b/test/cli/verilog/t_inst_signed1.v new file mode 100644 index 00000000..a1b1e4d5 --- /dev/null +++ b/test/cli/verilog/t_inst_signed1.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg signed i; + wire signed o1; + wire signed o2; + + integer cyc; initial cyc=0; + + sub1 sub1 (.i(i), .o(o1)); + sub2 sub2 (.i(o1), .o(o2)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + i <= 1'b0; + end + else if (cyc==1) begin + if (o2 != 1'b0) $stop; + i <= 1'b1; + end + else if (cyc==2) begin + if (o2 != 1'b1) $stop; + end + if (cyc==3) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +//msg2540 +module sub1 ( + input signed i, + output wire signed o); + assign o = ~i; +endmodule + +module sub2 (i,o); + input signed i; + output signed o; + wire signed o = ~i; +endmodule diff --git a/test/cli/verilog/t_inst_slice.v b/test/cli/verilog/t_inst_slice.v new file mode 100644 index 00000000..1a56b626 --- /dev/null +++ b/test/cli/verilog/t_inst_slice.v @@ -0,0 +1,85 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Varun Koyyalagunta. +// SPDX-License-Identifier: CC0-1.0 + +// bug1015 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [1:0] i = crc[1:0]; + logic [1:0] o [13:10] ; + + Test test (/*AUTOINST*/ + // Outputs + .o (o/*[1:0].[3:0]*/), + // Inputs + .i (i[1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hb42b2f48a0a9375a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + output logic [1:0] o [3:0], + //but this works + //logic [N-1:0] o + input [1:0] i); + + parameter N = 4; + + logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; + + sub sub [N-1:0] (.o (o), // many-to-many + .a (a), // many-to-many + .i (i)); // many-to-one +endmodule + +module sub + ( + input logic [1:0] i, + input logic [1:0] a, + output logic [1:0] o + ); + assign o = i + a; +endmodule diff --git a/test/cli/verilog/t_inst_slice_part_select.v b/test/cli/verilog/t_inst_slice_part_select.v new file mode 100644 index 00000000..3c837e0d --- /dev/null +++ b/test/cli/verilog/t_inst_slice_part_select.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by engr248. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + wire [31:0] in = 0; + wire [31:0] out; + + Test test( + .out(out[31:0]), + .clk(clk), + .in (in[31:0]) + ); + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +interface Intf (); +endinterface + +module Select + #( + parameter int NUM_MASTER = 1 + ) + ( + Intf Upstream, + Intf Downstream[NUM_MASTER] + ); +endmodule + +module Crossbar + #( + parameter int NUM_MASTER = 1, + parameter int NUM_SLAVE = 1 + ) + ( + Intf Masters[NUM_MASTER] + ); + + Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0](); + + + genvar i; + + for (i = 0; i < NUM_MASTER; i = i + 1) begin + Select #( + .NUM_MASTER(NUM_SLAVE) + ) + select_inst ( + .Upstream(Masters[i]), + // Following line seems to trigger a bad calculation for dimension where port + // is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE + .Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)]) + // The following line works as intended and should be functionally identical to the above line +// .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)]) + ); + end + +endmodule + +module Test + ( + input clk, + input [31:0] in, + output reg [31:0] out + ); + + always @(posedge clk) begin + out <= in; + end + + Intf MST[10](); + + Crossbar #( + .NUM_MASTER(10), + .NUM_SLAVE(1) + ) + xbar_inst ( + .Masters(MST) + ); + +endmodule diff --git a/test/cli/verilog/t_inst_tree.v b/test/cli/verilog/t_inst_tree.v new file mode 100644 index 00000000..ea4ab1d3 --- /dev/null +++ b/test/cli/verilog/t_inst_tree.v @@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // verilator lint_off GENCLK + reg printclk; + // verilator lint_on GENCLK + ps ps (printclk); + + reg [7:0] a; + wire [7:0] z; + + l1 u (~a,z); + + always @ (posedge clk) begin + printclk <= 0; + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + printclk <= 1'b1; + end + if (cyc==2) begin + a <= 8'b1; + end + if (cyc==3) begin + if (z !== 8'hf8) $stop; + //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; + //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; + //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; + //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; + //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; + //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module ps (input printclk); + // Check that %m stays correct across inlines + always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); +endmodule + +module l1 (input [7:0] a, output [7:0] z); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + l2 u0 (a, z0); l2 u1 (a, z1); +endmodule + +module l2 (input [7:0] a, output [7:0] z); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l3 u0 (a, z0); l3 u1 (a1, z1); +endmodule + +module l3 (input [7:0] a, output [7:0] z); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l4 u0 (a, z0); l4 u1 (a1, z1); +endmodule + +module l4 (input [7:0] a, output [7:0] z); + wire [7:0] z0; wire [7:0] z1; + assign z = z0+z1; + wire [7:0] a1 = a+8'd1; + l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); +endmodule + +module l5 (input [7:0] a, output [7:0] z); + parameter PARAM = 5; + wire [7:0] z0; wire [7:0] z1; + assign z = a; +endmodule diff --git a/test/cli/verilog/t_interface1.v b/test/cli/verilog/t_interface1.v new file mode 100644 index 00000000..56922208 --- /dev/null +++ b/test/cli/verilog/t_interface1.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Very simple test for interface pathclearing + +interface ifc; + logic [3:0] value; +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc itop(); + + sub c1 (.isub(itop), + .i_value(4'h4)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison + if (itop.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + ( + ifc isub, + input logic [3:0] i_value + ); + + always @* begin + isub.value = i_value; + end +endmodule : sub diff --git a/test/cli/verilog/t_interface1_modport.v b/test/cli/verilog/t_interface1_modport.v new file mode 100644 index 00000000..42ec3a82 --- /dev/null +++ b/test/cli/verilog/t_interface1_modport.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Very simple test for interface pathclearing + +interface ifc; + integer hidden_from_isub; + integer value; + modport out_modport (output value); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc itop(); + + sub c1 (.isub(itop), + .i_value(4)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop.value != 4) $stop; + itop.hidden_from_isub = 20; + if (itop.hidden_from_isub != 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub +`ifdef NANSI // bug868 + ( + isub, i_value + ); + ifc.out_modport isub; // Note parenthesis are not legal here + input integer i_value; +`else + ( + ifc.out_modport isub, + input integer i_value + ); +`endif + + always @* begin + isub.value = i_value; + end +endmodule diff --git a/test/cli/verilog/t_interface_ar2a.v b/test/cli/verilog/t_interface_ar2a.v new file mode 100644 index 00000000..f0c40684 --- /dev/null +++ b/test/cli/verilog/t_interface_ar2a.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: SystemVerilog interface test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Thierry Tambe. +// SPDX-License-Identifier: CC0-1.0 + +module t (); + + ahb_slave_intf AHB_S[1](); + + AHB_MEM uMEM(.S(AHB_S[0].source)); +// AHB_MEM V_MEM(.S(AHB_S[0])); + +endmodule + +module AHB_MEM + ( + ahb_slave_intf.source S + ); + +endmodule + +interface ahb_slave_intf + (); + + logic [31:0] HADDR; + + modport source (input HADDR); + +endinterface diff --git a/test/cli/verilog/t_interface_ar2b.v b/test/cli/verilog/t_interface_ar2b.v new file mode 100644 index 00000000..b14ae8cb --- /dev/null +++ b/test/cli/verilog/t_interface_ar2b.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: SystemVerilog interface test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Thierry Tambe. +// SPDX-License-Identifier: CC0-1.0 + +module t (); + + sub sub [1] (); + + ahb_slave_intf AHB_S[1](); + + AHB_MEM uMEM(.S(AHB_S[0])); +// AHB_MEM uMEM(.S(AHB_S[0].source)); + +endmodule + +module sub; +endmodule + +module AHB_MEM + ( + ahb_slave_intf.source S + ); + +endmodule + +interface ahb_slave_intf + (); + + logic [31:0] HADDR; + + modport source (input HADDR); + +endinterface diff --git a/test/cli/verilog/t_interface_gen.v b/test/cli/verilog/t_interface_gen.v new file mode 100644 index 00000000..f4f8511f --- /dev/null +++ b/test/cli/verilog/t_interface_gen.v @@ -0,0 +1,88 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Very simple test for interface pathclearing + +`ifdef VCS + `define UNSUPPORTED_MOD_IN_GENS +`endif +`ifdef VERILATOR + `define UNSUPPORTED_MOD_IN_GENS +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(1) itopa(); + ifc #(2) itopb(); + + sub #(1) ca (.isub(itopa), + .i_value(4)); + sub #(2) cb (.isub(itopb), + .i_value(5)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; + end + if (cyc==20) begin + if (itopa.get_value() != 4) $stop; + if (itopb.get_value() != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + #(parameter MODE = 0) + ( + ifc.out_modport isub, + input integer i_value + ); + +`ifdef UNSUPPORTED_MOD_IN_GENS + always @* isub.value = i_value; +`else + generate if (MODE == 1) begin + always @* isub.valuea = i_value; + end + else if (MODE == 2) begin + always @* isub.valueb = i_value; + end + endgenerate +`endif + +endmodule + +interface ifc; + parameter MODE = 0; + // Modports under generates not supported by all commercial simulators +`ifdef UNSUPPORTED_MOD_IN_GENS + integer value; + modport out_modport (output value); + function integer get_value(); return value; endfunction +`else + generate if (MODE == 0) begin + integer valuea; + modport out_modport (output valuea); + function integer get_valuea(); return valuea; endfunction + end + else begin + integer valueb; + modport out_modport (output valueb); + function integer get_valueb(); return valueb; endfunction + end + endgenerate +`endif +endinterface diff --git a/test/cli/verilog/t_interface_gen12.v b/test/cli/verilog/t_interface_gen12.v new file mode 100644 index 00000000..bbf87fff --- /dev/null +++ b/test/cli/verilog/t_interface_gen12.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// bug1005 + +module foo_module; + generate + for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block + logic baz; + end + endgenerate +endmodule + +module bar_module; + foo_module foo(); +endmodule + +module t; + bar_module bar(); + initial begin + bar.foo.my_gen_block[0].baz = 1; + if (bar.foo.my_gen_block[0].baz) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_interface_gen4.v b/test/cli/verilog/t_interface_gen4.v new file mode 100644 index 00000000..2c370310 --- /dev/null +++ b/test/cli/verilog/t_interface_gen4.v @@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug789 generates + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(1) itopa(); + ifc #(2) itopb(); + + sub #(1) ca (.isub(itopa), + .i_value(4)); + sub #(2) cb (.isub(itopb), + .i_value(5)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==1) begin + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; + end + if (cyc==20) begin + if (itopa.i != 4) $stop; + if (itopb.i != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub + #(parameter MODE = 0) + ( + ifc isub, + input integer i_value + ); + + // Commercial unsupported Xmrs into scopes within interfaces + generate + always_comb isub.i = i_value; + endgenerate +endmodule + +interface ifc; + parameter MODE = 0; + // Commercial unsupported Xmrs into scopes within interfaces + generate + integer i; + endgenerate +endinterface diff --git a/test/cli/verilog/t_interface_gen5.v b/test/cli/verilog/t_interface_gen5.v new file mode 100644 index 00000000..584db2bf --- /dev/null +++ b/test/cli/verilog/t_interface_gen5.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// bug998 + +interface intf + #(parameter PARAM = 0) + (); + logic val; + function integer func (); return 5; endfunction +endinterface + +module t1(intf mod_intf); + initial begin + $display("%m %d", mod_intf.val); + end +endmodule + +module t(); + generate + begin : TestIf + intf #(.PARAM(1)) my_intf (); + assign my_intf.val = '0; + t1 t (.mod_intf(my_intf)); +// initial $display("%0d", my_intf.func()); + end + endgenerate + + generate + begin + intf #(.PARAM(1)) my_intf (); + assign my_intf.val = '1; + t1 t (.mod_intf(my_intf)); +// initial $display("%0d", my_intf.func()); + end + endgenerate + + localparam LP = 1; + logic val; + + generate begin + if (LP) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + assign val = my_intf.val; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '1; + assign val = my_intf.val; + end + end endgenerate + + initial begin + $display("%0d", val); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_interface_gen6.v b/test/cli/verilog/t_interface_gen6.v new file mode 100644 index 00000000..4b7ef5de --- /dev/null +++ b/test/cli/verilog/t_interface_gen6.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// bug1001 + +interface intf + #(parameter PARAM = 0) + (); + logic val; +endinterface + +module t(); + + generate + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + endgenerate + + generate + begin + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + end + endgenerate + + generate + begin + begin + if (1) begin + intf #(.PARAM(2)) my_intf (); + assign my_intf.val = '1; + end else begin + intf #(.PARAM(3)) my_intf (); + assign my_intf.val = '0; + end + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_interface_modport_import.v b/test/cli/verilog/t_interface_modport_import.v new file mode 100644 index 00000000..57363e22 --- /dev/null +++ b/test/cli/verilog/t_interface_modport_import.v @@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the import parameter used with modport +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +interface test_if; + + // Interface variable + logic data; + + // Modport + modport mp( + import myfunc, + output data + ); + + function automatic logic myfunc (input logic val); + begin + myfunc = (val == 1'b0); + end + endfunction + +endinterface // test_if + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + test_if i (); + + testmod testmod_i (.clk (clk), + .i (i.mp)); + +endmodule + + +module testmod + ( + input clk, + test_if.mp i + ); + + always @(posedge clk) begin + i.data = 1'b0; + if (i.myfunc (1'b0)) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end +endmodule diff --git a/test/cli/verilog/t_interface_modportlist.v b/test/cli/verilog/t_interface_modportlist.v new file mode 100644 index 00000000..c72fa490 --- /dev/null +++ b/test/cli/verilog/t_interface_modportlist.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Adrian Wise. +// SPDX-License-Identifier: CC0-1.0 + +//bug1246 + +module t(input clk); + my_interface iface(); + my_module m(.clk(clk), iface); +endmodule + +module my_module(input clk, my_interface.my_port iface); + always @(posedge clk) begin + iface.b <= iface.a; + iface.c <= iface.a; + end +endmodule + +interface my_interface; + logic a, b, c; + modport my_port(input a, output b, c); +endinterface diff --git a/test/cli/verilog/t_interface_param1.v b/test/cli/verilog/t_interface_param1.v new file mode 100644 index 00000000..bed33ea7 --- /dev/null +++ b/test/cli/verilog/t_interface_param1.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 + +//bug692 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input wire clk; + + wire [31:0] result; + test_if #(.id(3)) s(); + sub_test U_SUB_TEST(s.a.b, result); // the line causing error +endmodule : t + +// --------------------------------------------------------------------------- + +module sub_test + ( + input [31:0] b, + output [31:0] c + ); + assign c = b; +endmodule + +// --------------------------------------------------------------------------- + +interface test_if + #(parameter id = 0) + (); + + typedef struct packed { + logic a; + logic [31:0] b; + } aType; + + aType a; + + typedef struct packed { + logic c; + logic [31:0] d; + } bType; + + bType b; + + modport master (input a, output b); + +endinterface diff --git a/test/cli/verilog/t_interface_parameter_access.v b/test/cli/verilog/t_interface_parameter_access.v new file mode 100644 index 00000000..4bdd8c6e --- /dev/null +++ b/test/cli/verilog/t_interface_parameter_access.v @@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Interface parameter getter +// +// A test of the import parameter used with modport +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader +// SPDX-License-Identifier: CC0-1.0 + +interface test_if #(parameter integer FOO = 1); + + // Interface variable + logic data; + + localparam integer BAR = FOO + 1; + + // Modport + modport mp( + import getFoo, + output data + ); + + function integer getFoo (); + return FOO; + endfunction + +endinterface // test_if + +function integer identity (input integer x); + return x; +endfunction + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + test_if #( .FOO (identity(5)) ) the_interface (); + test_if #( .FOO (identity(7)) ) array_interface [1:0] (); + + testmod testmod_i (.clk (clk), + .intf (the_interface), + .intf_no_mp (the_interface), + .intf_array (array_interface) + ); + + localparam THE_TOP_FOO = the_interface.FOO; + localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO}); + localparam THE_ARRAY_FOO = array_interface[0].FOO; + + initial begin + if (THE_TOP_FOO != 5) begin + $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); + $stop; + end + if (THE_TOP_FOO_BITS != 64) begin + $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); + $stop; + end + if (THE_ARRAY_FOO != 7) begin + $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); + $stop; + end + end + +endmodule + + +module testmod + ( + input clk, + test_if.mp intf, + test_if intf_no_mp, + test_if.mp intf_array [1:0] + ); + + localparam THE_FOO = intf.FOO; + localparam THE_OTHER_FOO = intf_no_mp.FOO; + localparam THE_ARRAY_FOO = intf_array[0].FOO; + localparam THE_BAR = intf.BAR; + localparam THE_OTHER_BAR = intf_no_mp.BAR; + localparam THE_ARRAY_BAR = intf_array[0].BAR; + + always @(posedge clk) begin + if (THE_FOO != 5) begin + $display("%%Error: THE_FOO = %0d", THE_FOO); + $stop; + end + if (THE_OTHER_FOO != 5) begin + $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); + $stop; + end + if (THE_ARRAY_FOO != 7) begin + $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); + $stop; + end + if (intf.FOO != 5) begin + $display("%%Error: intf.FOO = %0d", intf.FOO); + $stop; + end + if (intf_no_mp.FOO != 5) begin + $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); + $stop; + end + if (intf_array[0].FOO != 7) begin + $display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO); + $stop; + end + // if (i.getFoo() != 5) begin + // $display("%%Error: i.getFoo() = %0d", i.getFoo()); + // $stop; + // end + if (THE_BAR != 6) begin + $display("%%Error: THE_BAR = %0d", THE_BAR); + $stop; + end + if (THE_OTHER_BAR != 6) begin + $display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR); + $stop; + end + if (THE_ARRAY_BAR != 8) begin + $display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR); + $stop; + end + if (intf.BAR != 6) begin + $display("%%Error: intf.BAR = %0d", intf.BAR); + $stop; + end + if (intf_no_mp.BAR != 6) begin + $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); + $stop; + end + if (intf_array[0].BAR != 8) begin + $display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_interface_twod.v b/test/cli/verilog/t_interface_twod.v new file mode 100644 index 00000000..76b8a9a7 --- /dev/null +++ b/test/cli/verilog/t_interface_twod.v @@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +interface ifc; + integer value; + modport i (output value); + modport o (input value); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=1; + + ifc itop1a(), + itop1b(); + + wrapper c1 (.isuba(itop1a), + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module wrapper + ( + ifc.i isuba, isubb, + input integer i_valuea, i_valueb + ); + always @* begin + isuba.value = i_valuea; + isubb.value = i_valueb; + end +endmodule diff --git a/test/cli/verilog/t_langext_1.v b/test/cli/verilog/t_langext_1.v new file mode 100644 index 00000000..dfbef20d --- /dev/null +++ b/test/cli/verilog/t_langext_1.v @@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog1995ext+ and +verilog2001ext+ flags. +// +// This source code contains constructs that are valid in Verilog 2001 and +// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we +// set the language to be 1995, but not 2001. +// +// Compile only test, so no need for "All Finished" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [1:0] res; + + // Instantiate the test + test test_i (// Outputs + .res (res[1:0]), + // Inputs + .clk (clk), + .in (1'b1)); + +endmodule + +module test (// Outputs + res, + // Inputs + clk, + in + ); + output reg [1:0] res; + input clk; + input in; + + // This is a Verilog 2001 test + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + res[i:i] <= in; + end + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_langext_2.v b/test/cli/verilog/t_langext_2.v new file mode 100644 index 00000000..feac45c8 --- /dev/null +++ b/test/cli/verilog/t_langext_2.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +1364-1995ext+ and +systemverilogext+ flags. +// +// This source code contains constructs that are valid in SystemVerilog 2009 +// but not in Verilog 1995. So it should fail if we set the language to be +// Verilog 1995, but not SystemVerilog 2009. +// +// Compile only test, so no need for "All Finished" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [1:0] res; + + + // Instantiate the test + test test_i (/*AUTOINST*/ + // Outputs + .res (res), + // Inputs + .clk (clk), + .in (1'b1)); + +endmodule + +module test (// Outputs + res, + // Inputs + clk, + in + ); + output [1:0] res; + input clk; + input in; + + // This is a SystemVerilog 2009 only test + generate + genvar i; + for (i=0; i<2; i=i+1) begin + always @(posedge clk) begin + unique0 case (i) + 0: res[0:0] <= in; + 1: res[1:1] <= in; + endcase + end + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_langext_3.v b/test/cli/verilog/t_langext_3.v new file mode 100644 index 00000000..8efa0085 --- /dev/null +++ b/test/cli/verilog/t_langext_3.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog2001ext+ and +verilog2005ext+ flags. +// +// This source code uses the uwire declaration, which is only valid in Verilog +// 2005. +// +// Compile only test, so no need for "All Finished" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + uwire w; // Only in Verilog 2005 + +endmodule diff --git a/test/cli/verilog/t_math_cmp.v b/test/cli/verilog/t_math_cmp.v new file mode 100644 index 00000000..bf5dc80e --- /dev/null +++ b/test/cli/verilog/t_math_cmp.v @@ -0,0 +1,169 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [2:0] index_a; + reg [2:0] index_b; + + prover #(4) p4 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(32) p32 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(63) p63 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(64) p64 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(72) p72 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(126) p126 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + prover #(128) p128 (/*AUTOINST*/ + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); + + integer cyc; initial cyc=0; + initial index_a = 3'b0; + initial index_b = 3'b0; + always @* begin + index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4; + index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4; + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module prover ( + input clk, + input [2:0] index_a, + input [2:0] index_b + ); + + parameter WIDTH = 4; + + + reg signed [WIDTH-1:0] as; + reg signed [WIDTH-1:0] bs; + wire [WIDTH-1:0] b = bs; + + // verilator lint_off LATCH + always @* begin + casez (index_a) + 3'd0: as = {(WIDTH){1'd0}}; // 0 + 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 + 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv + 3'd3: as = {(WIDTH){1'd1}}; // -1 + 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv + default: $stop; + endcase + casez (index_b) + 3'd0: bs = {(WIDTH){1'd0}}; // 0 + 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 + 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv + 3'd3: bs = {(WIDTH){1'd1}}; // -1 + 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv + default: $stop; + endcase + end + // verilator lint_on LATCH + + reg [7:0] results[4:0][4:0]; + + wire gt = as>b; + wire gts = as>bs; + wire gte = as>=b; + wire gtes = as>=bs; + wire lt = as2) begin +`ifdef TEST_VERBOSE + $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", + index_a, index_b, + gt, gts, gte, gtes, lt, lts, lte, ltes); +`endif + exp = results[index_a][index_b]; + got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; + if (exp !== got) begin + $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); + $stop; + end + end + end + + // Result table + initial begin + // Indexes: 0, 1, -1, 127, -128 + // Gt Gts Gte Gtes Lt Lts Lte Ltes + results[0][0] = 8'b0_0_1_1_0_0_1_1; + results[0][1] = 8'b0_0_0_0_1_1_1_1; + results[0][2] = 8'b0_0_1_1_0_0_1_1; + results[0][3] = 8'b0_1_0_1_1_0_1_0; + results[0][4] = 8'b0_1_0_1_1_0_1_0; + results[1][0] = 8'b1_1_1_1_0_0_0_0; + results[1][1] = 8'b0_0_1_1_0_0_1_1; + results[1][2] = 8'b1_1_1_1_0_0_0_0; + results[1][3] = 8'b0_1_0_1_1_0_1_0; + results[1][4] = 8'b0_1_0_1_1_0_1_0; + results[2][0] = 8'b0_0_1_1_0_0_1_1; + results[2][1] = 8'b0_0_0_0_1_1_1_1; + results[2][2] = 8'b0_0_1_1_0_0_1_1; + results[2][3] = 8'b0_1_0_1_1_0_1_0; + results[2][4] = 8'b0_1_0_1_1_0_1_0; + results[3][0] = 8'b1_0_1_0_0_1_0_1; + results[3][1] = 8'b1_0_1_0_0_1_0_1; + results[3][2] = 8'b1_0_1_0_0_1_0_1; + results[3][3] = 8'b0_0_1_1_0_0_1_1; + results[3][4] = 8'b1_1_1_1_0_0_0_0; + results[4][0] = 8'b1_0_1_0_0_1_0_1; + results[4][1] = 8'b1_0_1_0_0_1_0_1; + results[4][2] = 8'b1_0_1_0_0_1_0_1; + results[4][3] = 8'b0_0_0_0_1_1_1_1; + results[4][4] = 8'b0_0_1_1_0_0_1_1; + end + +endmodule diff --git a/test/cli/verilog/t_math_concat.v b/test/cli/verilog/t_math_concat.v new file mode 100644 index 00000000..a70ec1af --- /dev/null +++ b/test/cli/verilog/t_math_concat.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [255:0] i; + wire [255:0] q; + + assign q = { + i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], + i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], + i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], + i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], + i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], + i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], + i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], + i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], + i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], + i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], + i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], + i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], + i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], + i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], + i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], + i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], + i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], + i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], + i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], + i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], + i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], + i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], + i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], + i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], + i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], + i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], + i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], + i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], + i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], + i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], + i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], + i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] + }; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%x %x\n", q, i); +`endif + if (cyc==1) begin + i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + end + if (cyc==2) begin + i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; + end + if (cyc==3) begin + if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_math_concat0.v b/test/cli/verilog/t_math_concat0.v new file mode 100644 index 00000000..fd18e18a --- /dev/null +++ b/test/cli/verilog/t_math_concat0.v @@ -0,0 +1,88 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [15:0] in = crc[15:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] outa; // From test of Test.v + wire [15:0] outb; // From test of Test.v + wire [15:0] outc; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .outa (outa[15:0]), + .outb (outb[15:0]), + .outc (outc[15:0]), + // Inputs + .clk (clk), + .in (in[15:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {16'h0, outa, outb, outc}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h09be74b1b0f8c35d + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + outa, outb, outc, + // Inputs + clk, in + ); + + input clk; + input [15:0] in; + output reg [15:0] outa; + output reg [15:0] outb; + output reg [15:0] outc; + + parameter WIDTH = 0; + always @(posedge clk) begin + outa <= {in}; + outb <= {{WIDTH{1'b0}}, in}; + outc <= {in, {WIDTH{1'b0}}}; + end +endmodule diff --git a/test/cli/verilog/t_math_concat64.v b/test/cli/verilog/t_math_concat64.v new file mode 100644 index 00000000..54f1ec60 --- /dev/null +++ b/test/cli/verilog/t_math_concat64.v @@ -0,0 +1,131 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [127:0] i; + wire [127:0] q1; + wire [127:0] q32; + wire [127:0] q64; + wire [63:0] q64_low; + + assign q1 = { + i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], + i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], + i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], + i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], + + i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], + i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], + i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], + i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1], + + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], + + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + assign q64[127:64] = { + i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], + i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], + i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], + i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], + + i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], + i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], + i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], + i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; + assign q64[63:0] = { + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], + + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + assign q64_low = { + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], + + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + assign q32[127:96] = { + i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], + i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], + i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], + i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]}; + assign q32[95:64] = { + i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], + i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], + i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], + i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; + assign q32[63:32] = { + i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], + i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], + i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], + i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]}; + assign q32[31:0] = { + i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], + i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], + i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], + i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%x %x\n", q1, i); +`endif + if (cyc==1) begin + i <= 128'hed388e646c843d35de489bab2413d770; + end + if (cyc==2) begin + i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; + if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==3) begin + i <= 128'he236ddfddddbdad20a48e039c9f395b8; + if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==4) begin + i <= 128'h45e0eb7642b148537491f3da147e7f26; + if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_math_cond_clean.v b/test/cli/verilog/t_math_cond_clean.v new file mode 100644 index 00000000..ca804c67 --- /dev/null +++ b/test/cli/verilog/t_math_cond_clean.v @@ -0,0 +1,95 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] cnt = crc[3:0]; + wire [6:0] decr = crc[14:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] next; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .next (next[3:0]), + // Inputs + .cnt (cnt[3:0]), + .decr (decr[6:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, next}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h7cd85c944415d2ef + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + next, + // Inputs + cnt, decr + ); + + input [3:0] cnt; + input signed [6:0] decr; + output reg [3:0] next; + + always_comb begin + reg signed [6:0] tmp; + tmp = 0; + // verilator lint_off WIDTH + tmp = ($signed({1'b0, cnt}) - decr); + // verilator lint_on WIDTH + if ((tmp > 15)) begin + next = 15; + end + else if ((tmp < 0)) begin + next = 0; + end + else begin + next = tmp[3:0]; + end + end + +endmodule diff --git a/test/cli/verilog/t_math_eq.v b/test/cli/verilog/t_math_eq.v new file mode 100644 index 00000000..13f0f866 --- /dev/null +++ b/test/cli/verilog/t_math_eq.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h1a0d07009b6a30d2 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output [3:0] out; + + assign out[0] = in[3:0] ==? 4'b1001; + assign out[1] = in[3:0] !=? 4'b1001; + assign out[2] = in[3:0] ==? 4'bx01x; + assign out[3] = in[3:0] !=? 4'bx01x; + + wire signed [3:0] ins = in[3:0]; + + wire signed [3:0] outs; + + assign outs[0] = ins ==? 4'sb1001; + assign outs[1] = ins !=? 4'sb1001; + assign outs[2] = ins ==? 4'sbx01x; + assign outs[3] = ins !=? 4'sbx01x; + + always_comb if (out != outs) $stop; + +endmodule diff --git a/test/cli/verilog/t_math_equal.v b/test/cli/verilog/t_math_equal.v new file mode 100644 index 00000000..54968a26 --- /dev/null +++ b/test/cli/verilog/t_math_equal.v @@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer _mode; + + reg _guard1; + reg [127:0] r_wide0; + reg _guard2; + wire [63:0] r_wide1; + reg _guard3; + reg _guard4; + reg _guard5; + reg _guard6; + + assign r_wide1 = r_wide0[127:64]; + + // surefire lint_off STMINI + initial _mode = 0; + + always @ (posedge clk) begin + if (_mode==0) begin + $write("[%0t] t_equal: Running\n", $time); + _guard1 <= 0; + _guard2 <= 0; + _guard3 <= 0; + _guard4 <= 0; + _guard5 <= 0; + _guard6 <= 0; + + _mode<=1; + r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; + end + else if (_mode==1) begin + _mode<=2; + // + if (5'd10 != 5'b1010) $stop; + if (5'd10 != 5'd10) $stop; + if (5'd10 != 5'd1_0) $stop; + if (5'd10 != 5'ha) $stop; + if (5'd10 != 5'o12) $stop; + if (5'd10 != 5'o1_2) $stop; + if (5'd10 != 5'B 1010) $stop; + if (5'd10 != 5'B 10_10) $stop; + if (5'd10 != 5'D10) $stop; + if (5'd10 != 5'H a) $stop; + if (5'd10 != 5 'O 12) $stop; + if (24'h29cbb8 != 24'o12345670) $stop; + if (24'h29__cbb8 != 24'o123456__70) $stop; + if (6'b111xxx !== 6'o7x) $stop; + if (6'b111??? !== 6'o7?) $stop; + if (6'b111zzz !== 6'o7z) $stop; + // + if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; + if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; + if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin + $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_math_imm.v b/test/cli/verilog/t_math_imm.v new file mode 100644 index 00000000..6ef2eb10 --- /dev/null +++ b/test/cli/verilog/t_math_imm.v @@ -0,0 +1,114 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 +// +// Example module to create problem. +// +// generate a 64 bit value with bits +// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 +// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 +// all other bits zero. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [7:0] crc; + reg [63:0] sum; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] HighLogicImm; // From example of example.v + wire [63:0] LogicImm; // From example of example.v + wire [63:0] LowLogicImm; // From example of example.v + // End of automatics + + wire [5:0] LowMaskSel_Top = crc[5:0]; + wire [5:0] LowMaskSel_Bot = crc[5:0]; + wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]}; + wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]}; + + example example (/*AUTOINST*/ + // Outputs + .LogicImm (LogicImm[63:0]), + .LowLogicImm (LowLogicImm[63:0]), + .HighLogicImm (HighLogicImm[63:0]), + // Inputs + .LowMaskSel_Top (LowMaskSel_Top[5:0]), + .HighMaskSel_Top (HighMaskSel_Top[5:0]), + .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), + .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); + + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc, + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, + LowLogicImm, HighLogicImm, LogicImm); +`endif + if (cyc==0) begin + // Single case + crc <= 8'h0; + sum <= 64'h0; + end + else if (cyc==1) begin + // Setup + crc <= 8'hed; + sum <= 64'h0; + end + else if (cyc<90) begin + sum <= {sum[62:0],sum[63]} ^ LogicImm; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); + if (crc !== 8'b00111000) $stop; + if (sum !== 64'h58743ffa61e41075) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module example (/*AUTOARG*/ + // Outputs + LogicImm, LowLogicImm, HighLogicImm, + // Inputs + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot + ); + + input [5:0] LowMaskSel_Top, HighMaskSel_Top; + input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; + output [63:0] LogicImm; + + output [63:0] LowLogicImm, HighLogicImm; + + + wire [63:0] LowLogicImm, HighLogicImm; + + /* verilator lint_off UNSIGNED */ + /* verilator lint_off CMPCONST */ + genvar i; + generate + for (i=0;i<64;i=i+1) begin : MaskVal + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); + end + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); + end + end + endgenerate + /* verilator lint_on UNSIGNED */ + /* verilator lint_on CMPCONST */ + + assign LogicImm = LowLogicImm & HighLogicImm; +endmodule diff --git a/test/cli/verilog/t_math_imm2.v b/test/cli/verilog/t_math_imm2.v new file mode 100644 index 00000000..4a0bff5d --- /dev/null +++ b/test/cli/verilog/t_math_imm2.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 +// +// Example module to create problem. +// +// generate a 64 bit value with bits +// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 +// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 +// all other bits zero. + +module t_math_imm2 (/*AUTOARG*/ + // Outputs + LogicImm, LowLogicImm, HighLogicImm, + // Inputs + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot + ); + input [4:0] LowMaskSel_Top, HighMaskSel_Top; + input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; + output [63:0] LogicImm; + + output [63:0] LowLogicImm, HighLogicImm; + + /* verilator lint_off UNSIGNED */ + /* verilator lint_off CMPCONST */ + genvar i; + generate + for (i=0;i<64;i=i+1) begin : MaskVal + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); + end + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); + end + end + endgenerate + + assign LogicImm = LowLogicImm & HighLogicImm; +endmodule diff --git a/test/cli/verilog/t_math_msvc_64.v b/test/cli/verilog/t_math_msvc_64.v new file mode 100644 index 00000000..27d49b27 --- /dev/null +++ b/test/cli/verilog/t_math_msvc_64.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + reg [89:0] in; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [89:0] out; // From test of Test.v + wire [44:0] line0; + wire [44:0] line1; + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[89:0]), + .line0 (line0[44:0]), + .line1 (line1[44:0]), + // Inputs + .clk (clk), + .in (in[89:0])); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out); +`endif + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; + end + else if (cyc==10) begin + if (in==out) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("*-* Failed!! *-*\n"); + $finish; + end + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + line0, line1, out, + // Inputs + clk, in + ); + + input clk; + input [89:0] in; + + output reg [44:0] line0; + output reg [44:0] line1; + output reg [89:0] out; + + assign {line0,line1} = in; + always @(posedge clk) begin + out <= {line0,line1}; + end +endmodule diff --git a/test/cli/verilog/t_math_mul.v b/test/cli/verilog/t_math_mul.v new file mode 100644 index 00000000..f83c751e --- /dev/null +++ b/test/cli/verilog/t_math_mul.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [31:0] out1; + wire [31:0] out2; + sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1}; + if (cyc==1) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc==90) begin + if (sum !== 64'he396068aba3898a2) $stop; + end + else if (cyc==91) begin + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in1, in2 + ); + + input [15:0] in1; + input [15:0] in2; + output reg signed [31:0] out1; + output reg unsigned [31:0] out2; + + always @* begin + // verilator lint_off WIDTH + out1 = $signed(in1) * $signed(in2); + out2 = $unsigned(in1) * $unsigned(in2); + // verilator lint_on WIDTH + end + +endmodule diff --git a/test/cli/verilog/t_math_pick.v b/test/cli/verilog/t_math_pick.v new file mode 100644 index 00000000..03ccdb90 --- /dev/null +++ b/test/cli/verilog/t_math_pick.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire pick1 = crc[0]; + wire [13:0][1:0] data1 = crc[27+1:1]; + wire [3:0][2:0][1:0] data2 = crc[23+29:29]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [15:0] [1:0] datao; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .datao (datao/*[15:0][1:0]*/), + // Inputs + .pick1 (pick1), + .data1 (data1/*[13:0][1:0]*/), + .data2 (data2/*[2:0][3:0][1:0]*/)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, datao}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3ff4bf0e6407b281 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + input logic pick1, + input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits + input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits + output logic [15:0] [1:0] datao // 16 x 2 = 32 bits + ); + // verilator lint_off WIDTH + always_comb datao[13: 0] // 28 bits + = (pick1) + ? {data1} // 28 bits + : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized + // verilator lint_on WIDTH + always_comb datao[15:14] = '0; +endmodule diff --git a/test/cli/verilog/t_math_real_public.v b/test/cli/verilog/t_math_real_public.v new file mode 100644 index 00000000..8f5e46fd --- /dev/null +++ b/test/cli/verilog/t_math_real_public.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Alex Solomatnikov +// SPDX-License-Identifier: CC0-1.0 + +module t; + sub #(.REAL(2.0)) sub; +endmodule + +module sub (); + parameter REAL = 0.0; + + initial begin + $display("REAL %g", REAL); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_math_red.v b/test/cli/verilog/t_math_red.v new file mode 100644 index 00000000..10cb292b --- /dev/null +++ b/test/cli/verilog/t_math_red.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + + reg [67:0] r; + + wire and_reduce = &r; + wire or_reduce = |r; + wire xor_reduce = ^r; + wire xnor_reduce = ~^r; + wire check_equal = r == 68'hffff_ffff_ffff_ffff_f; + + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x", + cyc, r, and_reduce, or_reduce, xor_reduce, check_equal); +`endif + cyc <= cyc + 1; + if (cyc == 1) begin + r <= 68'd0; + end + else if (cyc == 10) begin + `checkh(r, 68'h0000_0000_0000_0000_0); + `checkh(and_reduce, '0); + `checkh(or_reduce, '0); + `checkh(xor_reduce, '0); + `checkh(xnor_reduce, '1); + r <= 68'hffff_ffff_ffff_ffff_e; + end + else if (cyc == 11) begin + `checkh(r, 68'hffff_ffff_ffff_ffff_e); + `checkh(and_reduce, '0); + `checkh(or_reduce, '1); + `checkh(xor_reduce, '1); + `checkh(xnor_reduce, '0); + r <= 68'hffff_ffff_ffff_ffff_f; + end + else if (cyc == 12) begin + `checkh(r, 68'hffff_ffff_ffff_ffff_f); + `checkh(and_reduce, '1); + `checkh(or_reduce, '1); + `checkh(xor_reduce, '0); + `checkh(xnor_reduce, '1); + end + else if (cyc == 90) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + r <= 68'd0; + end + end +endmodule diff --git a/test/cli/verilog/t_math_repl.v b/test/cli/verilog/t_math_repl.v new file mode 100644 index 00000000..43b57e04 --- /dev/null +++ b/test/cli/verilog/t_math_repl.v @@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [63:0] rf; + reg [63:0] rf2; + reg [63:0] biu; + reg b; + + always @* begin + rf[63:32] = biu[63:32] & {32{b}}; + rf[31:0] = {32{b}}; + rf2 = rf; + rf2[31:0] = ~{32{b}}; + end + + reg [31:0] src1, src0, sr, mask; + wire [31:0] dualasr + = ((| src1[31:4]) + ? {{16{src0[31]}}, {16{src0[15]}}} + : ( ( sr & {2{mask[31:16]}}) + | ( {{16{src0[31]}}, {16{src0[15]}}} + & {2{~mask[31:16]}}))); + + wire [31:0] sl_mask + = (32'hffffffff << src1[4:0]); + + wire [31:0] sr_mask + = {sl_mask[0], sl_mask[1], + sl_mask[2], sl_mask[3], sl_mask[4], + sl_mask[5], sl_mask[6], sl_mask[7], + sl_mask[8], sl_mask[9], + sl_mask[10], sl_mask[11], + sl_mask[12], sl_mask[13], sl_mask[14], + sl_mask[15], sl_mask[16], + sl_mask[17], sl_mask[18], sl_mask[19], + sl_mask[20], sl_mask[21], + sl_mask[22], sl_mask[23], sl_mask[24], + sl_mask[25], sl_mask[26], + sl_mask[27], sl_mask[28], sl_mask[29], + sl_mask[30], sl_mask[31]}; + + wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; + wire [1:0] w = {2{b}}; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); +`endif + if (cyc==1) begin + biu <= 64'h12451282_abadee00; + b <= 1'b0; + src1 <= 32'h00000001; + src0 <= 32'h9a4f1235; + sr <= 32'h0f19f567; + mask <= 32'h7af07ab4; + end + if (cyc==2) begin + biu <= 64'h12453382_abad8801; + b <= 1'b1; + if (rf != 64'h0) $stop; + if (rf2 != 64'h00000000ffffffff) $stop; + src1 <= 32'h0010000f; + src0 <= 32'h028aa336; + sr <= 32'h42ad0377; + mask <= 32'h1ab3b906; + if (dualasr != 32'h8f1f7060) $stop; + if (sl_mask != 32'hfffffffe) $stop; + if (sr_mask != 32'h7fffffff) $stop; + if (widerep != '0) $stop; + end + if (cyc==3) begin + biu <= 64'h12422382_77ad8802; + b <= 1'b1; + if (rf != 64'h12453382ffffffff) $stop; + if (rf2 != 64'h1245338200000000) $stop; + src1 <= 32'h0000000f; + src0 <= 32'h5c158f71; + sr <= 32'h7076c40a; + mask <= 32'h33eb3d44; + if (dualasr != 32'h0000ffff) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + if (widerep != '1) $stop; + end + if (cyc==4) begin + if (rf != 64'h12422382ffffffff) $stop; + if (rf2 != 64'h1242238200000000) $stop; + if (dualasr != 32'h3062cc1e) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + $write("*-* All Finished *-*\n"); + if (widerep != '1) $stop; + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_math_reverse.v b/test/cli/verilog/t_math_reverse.v new file mode 100644 index 00000000..f8b6b8a2 --- /dev/null +++ b/test/cli/verilog/t_math_reverse.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [7:0] crc; + + // Build up assignments + wire [7:0] bitrev; + assign bitrev[7] = crc[0]; + assign bitrev[6] = crc[1]; + assign bitrev[5] = crc[2]; + assign bitrev[4] = crc[3]; + assign bitrev[0] = crc[7]; + assign bitrev[1] = crc[6]; + assign bitrev[2] = crc[5]; + assign bitrev[3] = crc[4]; + + // Build up always assignments + reg [7:0] bitrevb; + always @ (/*AS*/crc) begin + bitrevb[7] = crc[0]; + bitrevb[6] = crc[1]; + bitrevb[5] = crc[2]; + bitrevb[4] = crc[3]; + bitrevb[0] = crc[7]; + bitrevb[1] = crc[6]; + bitrevb[2] = crc[5]; + bitrevb[3] = crc[4]; + end + + // Build up always assignments + reg [7:0] bitrevr; + always @ (posedge clk) begin + bitrevr[7] <= crc[0]; + bitrevr[6] <= crc[1]; + bitrevr[5] <= crc[2]; + bitrevr[4] <= crc[3]; + bitrevr[0] <= crc[7]; + bitrevr[1] <= crc[6]; + bitrevr[2] <= crc[5]; + bitrevr[3] <= crc[4]; + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==1) begin + crc <= 8'hed; + end + if (cyc==2 && bitrev!=8'hb7) $stop; + if (cyc==3 && bitrev!=8'h5b) $stop; + if (cyc==4 && bitrev!=8'h2d) $stop; + if (cyc==5 && bitrev!=8'h16) $stop; + if (cyc==6 && bitrev!=8'h8b) $stop; + if (cyc==7 && bitrev!=8'hc5) $stop; + if (cyc==8 && bitrev!=8'he2) $stop; + if (cyc==9 && bitrev!=8'hf1) $stop; + if (bitrevb != bitrev) $stop; + if (cyc==3 && bitrevr!=8'hb7) $stop; + if (cyc==4 && bitrevr!=8'h5b) $stop; + if (cyc==5 && bitrevr!=8'h2d) $stop; + if (cyc==6 && bitrevr!=8'h16) $stop; + if (cyc==7 && bitrevr!=8'h8b) $stop; + if (cyc==8 && bitrevr!=8'hc5) $stop; + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_math_shift.v b/test/cli/verilog/t_math_shift.v new file mode 100644 index 00000000..e8f9379c --- /dev/null +++ b/test/cli/verilog/t_math_shift.v @@ -0,0 +1,239 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + ign, ign2, ign3, ign4, ign4s, + // Inputs + clk + ); + + input clk; + output [31:0] ign; + output [3:0] ign2; + output [11:0] ign3; + + parameter [95:0] P6 = 6; + localparam P64 = (1 << P6); + + // verilator lint_off WIDTH + localparam [4:0] PBIG23 = 1'b1 << ~73'b0; + localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; + // verilator lint_on WIDTH + + reg [31:0] iright; + reg signed [31:0] irights; + reg [31:0] ileft; + reg [P64-1:0] qright; + reg signed [P64-1:0] qrights; + reg [P64-1:0] qleft; + reg [95:0] wright; + reg signed [95:0] wrights; + reg [95:0] wleft; + + reg [31:0] q_iright; + reg signed [31:0] q_irights; + reg [31:0] q_ileft; + reg [P64-1:0] q_qright; + reg signed [P64-1:0] q_qrights; + reg [P64-1:0] q_qleft; + reg [95:0] q_wright; + reg signed [95:0] q_wrights; + reg [95:0] q_wleft; + + + reg [31:0] w_iright; + reg signed [31:0] w_irights; + reg [31:0] w_ileft; + reg [P64-1:0] w_qright; + reg signed [P64-1:0] w_qrights; + reg [P64-1:0] w_qleft; + reg [95:0] w_wright; + reg signed [95:0] w_wrights; + reg [95:0] w_wleft; + + reg [31:0] iamt; + reg [63:0] qamt; + reg [95:0] wamt; + + assign ign = {31'h0, clk} >>> 4'bx; // bug760 + assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 + assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, + iamt[1:0] >> {11{iamt[5:2]}}, + $signed(iamt[1:0]) >>> {22{iamt[5:2]}}, + $signed(iamt[1:0]) >>> {11{iamt[5:2]}}, + iamt[1:0] << {22{iamt[5:2]}}, + iamt[1:0] << {11{iamt[5:2]}}}; + + wire [95:0] wamtt = {iamt,iamt,iamt}; + output wire [95:0] ign4; + assign ign4 = wamtt >> {11{iamt[5:2]}}; + output wire signed [95:0] ign4s; + assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}}; + + always @* begin + iright = 32'h819b018a >> iamt; + irights = 32'sh819b018a >>> signed'(iamt); + ileft = 32'h819b018a << iamt; + qright = 64'hf784bf8f_12734089 >> iamt; + qrights = 64'shf784bf8f_12734089 >>> signed'(iamt); + qleft = 64'hf784bf8f_12734089 << iamt; + wright = 96'hf784bf8f_12734089_190abe48 >> iamt; + wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt); + wleft = 96'hf784bf8f_12734089_190abe48 << iamt; + + q_iright = 32'h819b018a >> qamt; + q_irights = 32'sh819b018a >>> signed'(qamt); + q_ileft = 32'h819b018a << qamt; + q_qright = 64'hf784bf8f_12734089 >> qamt; + q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt); + q_qleft = 64'hf784bf8f_12734089 << qamt; + q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt; + q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt); + q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt; + + w_iright = 32'h819b018a >> wamt; + w_irights = 32'sh819b018a >>> signed'(wamt); + w_ileft = 32'h819b018a << wamt; + w_qright = 64'hf784bf8f_12734089 >> wamt; + w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt); + w_qleft = 64'hf784bf8f_12734089 << wamt; + w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; + w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); + w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); +`endif + if (cyc==1) begin + iamt <= 0; + qamt <= 0; + wamt <= 0; + if (P64 != 64) $stop; + if (5'b10110>>2 != 5'b00101) $stop; + if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness + if (5'b10110<<2 != 5'b11000) $stop; + if (5'b10110<<<2 != 5'b11000) $stop; + if (5'sb10110>>2 != 5'sb00101) $stop; + if (5'sb10110>>>2 != 5'sb11101) $stop; + if (5'sb10110<<2 != 5'sb11000) $stop; + if (5'sb10110<<<2 != 5'sb11000) $stop; + // Allow >64 bit shifts if the shift amount is a constant + if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; + end + if (cyc==2) begin + iamt <= 28; + qamt <= 28; + wamt <= 28; + if (ileft != 32'h819b018a) $stop; + if (iright != 32'h819b018a) $stop; + if (irights != 32'h819b018a) $stop; + if (qleft != 64'hf784bf8f_12734089) $stop; + if (qright != 64'hf784bf8f_12734089) $stop; + if (qrights != 64'hf784bf8f_12734089) $stop; + if (wleft != 96'hf784bf8f12734089190abe48) $stop; + if (wright != 96'hf784bf8f12734089190abe48) $stop; + if (wrights != 96'hf784bf8f12734089190abe48) $stop; + end + if (cyc==3) begin + iamt <= 31; + qamt <= 31; + wamt <= 31; + if (ileft != 32'ha0000000) $stop; + if (iright != 32'h8) $stop; + if (irights != 32'hfffffff8) $stop; + if (qleft != 64'hf127340890000000) $stop; + if (qright != 64'h0000000f784bf8f1) $stop; + if (qrights != 64'hffffffff784bf8f1) $stop; + if (wleft != 96'hf12734089190abe480000000) $stop; + if (wright != 96'h0000000f784bf8f127340891) $stop; + if (wrights != 96'hffffffff784bf8f127340891) $stop; + end + if (cyc==4) begin + iamt <= 32; + qamt <= 32; + wamt <= 32; + if (ileft != 32'h0) $stop; + if (iright != 32'h1) $stop; + if (qleft != 64'h8939a04480000000) $stop; + if (qright != 64'h00000001ef097f1e) $stop; + end + if (cyc==5) begin + iamt <= 33; + qamt <= 33; + wamt <= 33; + if (ileft != 32'h0) $stop; + if (iright != 32'h0) $stop; + if (qleft != 64'h1273408900000000) $stop; + if (qright != 64'h00000000f784bf8f) $stop; + end + if (cyc==6) begin + iamt <= 64; + qamt <= 64; + wamt <= 64; + if (ileft != 32'h0) $stop; + if (iright != 32'h0) $stop; + if (qleft != 64'h24e6811200000000) $stop; + if (qright != 64'h000000007bc25fc7) $stop; + end + if (cyc==7) begin + iamt <= 128; + qamt <= 128; + wamt <= 128; + if (ileft != 32'h0) $stop; + if (iright != 32'h0) $stop; + if (qleft != 64'h0) $stop; + if (qright != 64'h0) $stop; + end + if (cyc==8) begin + iamt <= 100; + qamt <= {32'h10, 32'h0}; + wamt <= {32'h10, 64'h0}; + if (ileft != '0) $stop; + if (iright != '0) $stop; + if (irights != '1) $stop; + if (qleft != '0) $stop; + if (qright != '0) $stop; + if (qrights != '1) $stop; + if (wleft != '0) $stop; + if (wright != '0) $stop; + if (wrights != '1) $stop; + end + if (cyc==19) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // General rule to test all q's + if (cyc != 0) begin + if (ileft != q_ileft) $stop; + if (iright != q_iright) $stop; + if (irights != q_irights) $stop; + if (qleft != q_qleft) $stop; + if (qright != q_qright) $stop; + if (qrights != q_qrights) $stop; + if (wleft != q_wleft) $stop; + if (wright != q_wright) $stop; + if (wrights != q_wrights) $stop; + + if (ileft != w_ileft) $stop; + if (iright != w_iright) $stop; + if (irights != w_irights) $stop; + if (qleft != w_qleft) $stop; + if (qright != w_qright) $stop; + if (qrights != w_qrights) $stop; + if (wleft != w_wleft) $stop; + if (wright != w_wright) $stop; + if (wrights != w_wrights) $stop; + end + end + end +endmodule diff --git a/test/cli/verilog/t_math_shift_extend.v b/test/cli/verilog/t_math_shift_extend.v new file mode 100644 index 00000000..8e40234c --- /dev/null +++ b/test/cli/verilog/t_math_shift_extend.v @@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + logic in1 = 1; + logic [1:0] in2 = 2'b11; + logic [31:0] out; + logic [7:0] ones = 8'b11111111; + logic [9:0] ones10 = 10'b1111111111; + + typedef logic [7:0] data_t; + + typedef logic [9:0] ten_t; + ten_t out10; + + // verilator lint_off WIDTH + initial begin + in1 = 1; + in2 = 0; + out = data_t'(in1 << in2); + if (out != 8'b1) $stop; + + in2 = 1; + out = data_t'(in1 << in2); + if (out != 8'b10) $stop; + + in2 = 2; + out = data_t'(in1 << in2); + if (out != 8'b100) $stop; + + in2 = 3; + out = data_t'(in1 << in2); + if (out != 8'b1000) $stop; + + // Check upper bits get cleared when cast + in2 = 3; + out = data_t'(ones << in2); + if (out != 8'b11111000) $stop; + + in2 = 3; + out = data_t'(ones10 << in2); + if (out != 8'b11111000) $stop; + + // bug2597 + out = data_t'(10'h208 >> 2); + if (out != 8'h82) $stop; + + out = data_t'(10'h208 >> 2); + if (out != 8'h82) $stop; + + out = data_t'('h208 >> 2); + if (out != 8'h82) $stop; + + out10 = ten_t'('h404 >> 2); + if (out10 != 10'h101) $stop; + + $write("*-* All Finished *-*\n"); + $finish(); + end +endmodule diff --git a/test/cli/verilog/t_math_shift_rep.v b/test/cli/verilog/t_math_shift_rep.v new file mode 100644 index 00000000..cd0011fe --- /dev/null +++ b/test/cli/verilog/t_math_shift_rep.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + //bug765; disappears if add this wire + //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values + wire [7:0] a = crc[7:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [15:0] y; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .y (y[15:0]), + // Inputs + .a (a[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, y}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + y, + // Inputs + a + ); + input signed [7:0] a; + output [15:0] y; + // verilator lint_off WIDTH + assign y = ~66'd0 <<< {4{a}}; + // verilator lint_on WIDTH +endmodule diff --git a/test/cli/verilog/t_math_shift_sel.v b/test/cli/verilog/t_math_shift_sel.v new file mode 100644 index 00000000..e0b20211 --- /dev/null +++ b/test/cli/verilog/t_math_shift_sel.v @@ -0,0 +1,88 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [106:0] in = {~crc[42:0], crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] out1; // From test of Test.v + wire [7:0] out2; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out1 (out1[7:0]), + .out2 (out2[7:0]), + // Inputs + .in (in[106:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, out1, out1}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc746017202a24ecc + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input [106:0] in; + output [7:0] out1, out2; + + // verilator lint_off WIDTH + // Better written as onibble[99 +: 8]. Verilator will convert it. + wire [7:0] out1 = (in >>> 99) & 255; + // verilator lint_on WIDTH + wire [7:0] out2 = in[106:99]; + +endmodule diff --git a/test/cli/verilog/t_math_shiftrs.v b/test/cli/verilog/t_math_shiftrs.v new file mode 100644 index 00000000..d89c637d --- /dev/null +++ b/test/cli/verilog/t_math_shiftrs.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg signed [64+15:0] data; + integer i; + integer b; + reg signed [64+15:0] srs; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==2) begin + data <= 80'h0; + data[75] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc==3) begin + for (i=0; i<85; i=i+1) begin + srs = data>>>i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b=0; b<80; b=b+1) begin + if (srs[b] != (b==(75-i) || b==(10-i))) $stop; + end + end + end + if (cyc==10) begin + data <= 80'h0; + data[79] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc==12) begin + for (i=0; i<85; i=i+1) begin + srs = data>>>i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b=0; b<80; b=b+1) begin + if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; + end + end + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_math_sign_extend.v b/test/cli/verilog/t_math_sign_extend.v new file mode 100644 index 00000000..4ca6a714 --- /dev/null +++ b/test/cli/verilog/t_math_sign_extend.v @@ -0,0 +1,132 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test demonstrates an issue with sign extension. +// Assigning to localparms larger than 32 bits broke in 3.862 +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Mike Thyer. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + + localparam [ 0:0] one1_lp = 1; + localparam [ 1:0] one2_lp = 1; + localparam [ 2:0] one3_lp = 1; + localparam [ 3:0] one4_lp = 1; + localparam [ 4:0] one5_lp = 1; + localparam [ 5:0] one6_lp = 1; + localparam [ 6:0] one7_lp = 1; + localparam [ 7:0] one8_lp = 1; + localparam [ 8:0] one9_lp = 1; + localparam [ 9:0] one10_lp = 1; + localparam [19:0] one20_lp = 1; + localparam [29:0] one30_lp = 1; + localparam [30:0] one31_lp = 1; + localparam [31:0] one32_lp = 1; + localparam [32:0] one33_lp = 1; + localparam [33:0] one34_lp = 1; + localparam [34:0] one35_lp = 1; + localparam [35:0] one36_lp = 1; + localparam [36:0] one37_lp = 1; + localparam [37:0] one38_lp = 1; + localparam [38:0] one39_lp = 1; + localparam [39:0] one40_lp = 1; + localparam [49:0] one50_lp = 1; + localparam [59:0] one60_lp = 1; + localparam [60:0] one61_lp = 1; + localparam [61:0] one62_lp = 1; + localparam [62:0] one63_lp = 1; + localparam [63:0] one64_lp = 1; + localparam [64:0] one65_lp = 1; + localparam [65:0] one66_lp = 1; + localparam [66:0] one67_lp = 1; + localparam [67:0] one68_lp = 1; + localparam [68:0] one69_lp = 1; + localparam [69:0] one70_lp = 1; + + bit all_ok = 1; + + initial begin +`ifdef TEST_VERBOSE + $display("one1_lp : %x %d", one1_lp, one1_lp==1); + $display("one2_lp : %x %d", one2_lp, one2_lp==1); + $display("one3_lp : %x %d", one3_lp, one3_lp==1); + $display("one4_lp : %x %d", one4_lp, one4_lp==1); + $display("one5_lp : %x %d", one5_lp, one5_lp==1); + $display("one6_lp : %x %d", one6_lp, one6_lp==1); + $display("one7_lp : %x %d", one7_lp, one7_lp==1); + $display("one8_lp : %x %d", one8_lp, one8_lp==1); + $display("one9_lp : %x %d", one9_lp, one9_lp==1); + $display("one10_lp: %x %d", one10_lp, one10_lp==1); + $display("one20_lp: %x %d", one20_lp, one20_lp==1); + $display("one30_lp: %x %d", one30_lp, one30_lp==1); + $display("one31_lp: %x %d", one31_lp, one31_lp==1); + $display("one32_lp: %x %d", one32_lp, one32_lp==1); + $display("one33_lp: %x %d", one33_lp, one33_lp==1); + $display("one34_lp: %x %d", one34_lp, one34_lp==1); + $display("one35_lp: %x %d", one35_lp, one35_lp==1); + $display("one36_lp: %x %d", one36_lp, one36_lp==1); + $display("one37_lp: %x %d", one37_lp, one37_lp==1); + $display("one38_lp: %x %d", one38_lp, one38_lp==1); + $display("one39_lp: %x %d", one39_lp, one39_lp==1); + $display("one40_lp: %x %d", one40_lp, one40_lp==1); + $display("one50_lp: %x %d", one50_lp, one50_lp==1); + $display("one60_lp: %x %d", one60_lp, one60_lp==1); + $display("one61_lp: %x %d", one61_lp, one61_lp==1); + $display("one62_lp: %x %d", one62_lp, one62_lp==1); + $display("one63_lp: %x %d", one63_lp, one63_lp==1); + $display("one64_lp: %x %d", one64_lp, one64_lp==1); + $display("one65_lp: %x %d", one65_lp, one65_lp==1); + $display("one66_lp: %x %d", one66_lp, one66_lp==1); + $display("one67_lp: %x %d", one67_lp, one67_lp==1); + $display("one68_lp: %x %d", one68_lp, one68_lp==1); + $display("one69_lp: %x %d", one69_lp, one69_lp==1); + $display("one70_lp: %x %d", one70_lp, one70_lp==1); +`endif + + all_ok &= one1_lp == 1; + all_ok &= one2_lp == 1; + all_ok &= one3_lp == 1; + all_ok &= one4_lp == 1; + all_ok &= one5_lp == 1; + all_ok &= one6_lp == 1; + all_ok &= one7_lp == 1; + all_ok &= one8_lp == 1; + all_ok &= one9_lp == 1; + all_ok &= one10_lp == 1; + all_ok &= one20_lp == 1; + all_ok &= one30_lp == 1; + all_ok &= one31_lp == 1; + all_ok &= one32_lp == 1; + all_ok &= one33_lp == 1; + all_ok &= one34_lp == 1; + all_ok &= one35_lp == 1; + all_ok &= one36_lp == 1; + all_ok &= one37_lp == 1; + all_ok &= one38_lp == 1; + all_ok &= one39_lp == 1; + all_ok &= one40_lp == 1; + all_ok &= one50_lp == 1; + all_ok &= one60_lp == 1; + all_ok &= one61_lp == 1; + all_ok &= one62_lp == 1; + all_ok &= one63_lp == 1; + all_ok &= one64_lp == 1; + all_ok &= one65_lp == 1; + all_ok &= one66_lp == 1; + all_ok &= one67_lp == 1; + all_ok &= one68_lp == 1; + all_ok &= one69_lp == 1; + all_ok &= one70_lp == 1; + + if (!all_ok) $stop; + $write("*-* All Finished *-*\n"); + $finish; + + end +endmodule diff --git a/test/cli/verilog/t_math_signed2.v b/test/cli/verilog/t_math_signed2.v new file mode 100644 index 00000000..41337b3d --- /dev/null +++ b/test/cli/verilog/t_math_signed2.v @@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Peter Debacker. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [10:0] in; + reg signed[7:0] min; + reg signed[7:0] max; + wire signed[7:0] filtered_data; + reg signed[7:0] delay_minmax[31:0]; + integer k; + + initial begin + in = 11'b10000001000; + for(k=0;k<32;k=k+1) + delay_minmax[k] = 0; + end + + assign filtered_data = $signed(in[10:3]); + + always @(posedge clk) begin + in = in + 8; +`ifdef TEST_VERBOSE + $write("filtered_data: %d\n", filtered_data); +`endif + // delay line shift + for (k=31;k>0;k=k-1) begin + delay_minmax[k] = delay_minmax[k-1]; + end + delay_minmax[0] = filtered_data; +`ifdef TEST_VERBOSE + $write("delay_minmax[0] = %d\n", delay_minmax[0]); + $write("delay_minmax[31] = %d\n", delay_minmax[31]); +`endif + // find min and max + min = 127; + max = -128; +`ifdef TEST_VERBOSE + $write("max init: %d\n", max); + $write("min init: %d\n", min); +`endif + for(k=0;k<32;k=k+1) begin + if ((delay_minmax[k]) > $signed(max)) + max = delay_minmax[k]; + if ((delay_minmax[k]) < $signed(min)) + min = delay_minmax[k]; + end +`ifdef TEST_VERBOSE + $write("max: %d\n", max); + $write("min: %d\n", min); +`endif + if (min == 127) begin + $stop; + end + else if (filtered_data >= -61) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_math_signed3.v b/test/cli/verilog/t_math_signed3.v new file mode 100644 index 00000000..3deed359 --- /dev/null +++ b/test/cli/verilog/t_math_signed3.v @@ -0,0 +1,101 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/); + + // verilator lint_off WIDTH + wire [1:0] bug729_au = ~0; + wire signed [1:0] bug729_as = ~0; + wire [2:0] bug729_b = ~0; + // the $signed output is unsigned because the input is unsigned; the signedness does not change. + wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 + wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 + wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 + wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 + wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 + wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 + + wire [3:0] bug733_a = 4'b0010; + wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned + wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 + + wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 + wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 + + // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign + + wire [3:0] bug733_qu = 2'sb11; // 4'b1111 + wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 + reg signed [32:0] bug349_s; + reg signed [32:0] bug349_u; + + wire signed [1:0] sb11 = 2'sb11; + + wire [3:0] subout_u; + sub sub (.a(2'sb11), .z(subout_u)); + initial `checkh(subout_u, 4'b1111); + + wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; + initial `checkh(cond_a, 6'b111111); + wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; + initial `checkh(cond_b, 6'b111111); + + initial begin + // verilator lint_on WIDTH + `checkh(bug729_yuu, 1'b0); + `checkh(bug729_ysu, 1'b0); + `checkh(bug729_yus, 1'b1); + `checkh(bug729_yss, 1'b1); + + `checkh(bug729_zuu, 1'b0); + `checkh(bug729_zsu, 1'b0); + `checkh(bug729_zus, 1'b1); + `checkh(bug729_zss, 1'b1); + + `checkh(bug733_yu, 4'b1111); + `checkh(bug733_ys, 4'b1111); + + `checkh(bug733_zu, 4'b1111); + `checkh(bug733_zs, 4'b1111); + + `checkh(bug733_qu, 4'b1111); + `checkh(bug733_qs, 4'b1111); + + // verilator lint_off WIDTH + bug349_s = 4'sb1111; + `checkh(bug349_s, 33'h1ffffffff); + bug349_u = 4'sb1111; + `checkh(bug349_u, 33'h1ffffffff); + + bug349_s = 4'sb1111 - 1'b1; + `checkh(bug349_s,33'he); + + bug349_s = 4'sb1111 - 5'b00001; + `checkh(bug349_s,33'he); + + case (2'sb11) + 4'b1111: ; + default: $stop; + endcase + + case (sb11) + 4'b1111: ; + default: $stop; + endcase + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub (input [3:0] a, + output [3:0] z); + assign z = a; +endmodule diff --git a/test/cli/verilog/t_math_signed4.v b/test/cli/verilog/t_math_signed4.v new file mode 100644 index 00000000..0cec8a31 --- /dev/null +++ b/test/cli/verilog/t_math_signed4.v @@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) +`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) + +module t (/*AUTOARG*/); + + bit fail; + + localparam signed [3:0] bug737_p1 = 4'b1000; + + wire [3:0] bug737_a = 4'b1010; + reg [5:0] bug737_y; + reg signed [3:0] w4_s; + reg signed [4:0] w5_s; + reg [3:0] w4_u; + reg [4:0] w5_u; + reg signed [8:0] w9_s; + real r; + initial begin + // verilator lint_off WIDTH + bug737_y = bug737_a + (bug737_p1 + 4'sb0); + `checkh(bug737_y, 6'b010010); //bug737 + + // 6u +[6u] 4s +[6s] 6s + bug737_y = 6'b001010 + (4'sb1000 + 6'sb0); + `checkh(bug737_y, 6'b010010); //bug737, getx 000010 + + // 6u +[6u] 4s +[6s] 6s + bug737_y = 6'b001010 + (4'b1000 + 6'sb0); + `checkh(bug737_y, 6'b010010); //ok + + bug737_y = 6'b001010 + (6'sb111000 + 6'sb0); + `checkh(bug737_y, 6'b000010); //ok + + // v--- sign extends to 6-bits + bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0); + `checkh(bug737_y, 6'b000010); //ok + + // From t_math_signed_3 + w4_s = 4'sb1111 - 1'b1; + `checkh(w4_s,33'he); + + w4_s = 4'sb1111 - 5'b00001; + `checkh(w4_s,33'he); + + w4_s = 4'sb1111 - 1'sb1; + `checkh(w4_s,4'h0); + w5_s = 4'sb1111 - 1'sb1; + `checkh(w5_s,4'h0); + + w4_s = 4'sb1111 - 4'sb1111; + `checkh(w4_s,4'h0); + w5_s = 4'sb1111 - 4'sb1111; + `checkh(w5_s,5'h0); + + // The assign LHS being signed or unsigned does not matter per IEEE + // The upper add being signed DOES matter propagating to lower + w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add + `checkh(w4_s,4'he); + w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend + `checkh(w4_s,4'h0); + w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend + `checkh(w4_s,4'he); // BUG, Verilator says 'h0 + + w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS + `checkh(w5_u, 5'b10000); + w4_u = 4'b1111 + 4'b0001; // Normal case + `checkh(w4_u, 4'b0000); + + // Another example of promotion, the add is 4 bits wide + w4_u = 3'b111 + 3'b010; + `checkh(w4_u, 4'b1001); + // + w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter + `checkh(w4_u, 4'sb1111); + w4_s = 3'sb111 * 3'sb001; // Signed output + `checkh(w4_s, 4'sb1111); + w4_s = 3'b111 * 3'sb001; // Unsigned output + `checkh(w4_s, 4'b0111); + + // Conditionals get width from parent; are assignment-like + w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11); + `checkh(w4_u, 4'b0100); + w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000); + `checkh(w4_u, 4'b0000); + + // If RHS is larger, that larger size is used + w4_u = 5'b10000 / 5'b00100; + `checkh(w4_u, 4'b0100); + + // bug754 + w5_u = 4'sb0010 << -2'sd1; // << 3 +`ifdef VCS + `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug +`else + `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug +`endif + w5_u = 4'sb1000 << 0; // Sign extends + `checkh(w5_u, 5'b11000); + + // Reals do not propagate to children + r = 1.0 + ( 1 + (1 / 2)); + `checkf(r, 2.0); + + // Self determined sign extension + r = $itor(3'sb111); + `checkf(r, -1.0); + + // If any part of case is real, all is real + case (22) + 22.0: ; + 22.1: $stop; + default: $stop; + endcase + + // bug759 + w5_u = { -4'sd7 }; + `checkh(w5_u, 5'b01001); + w5_u = {2{ -2'sd1 }}; + `checkh(w5_u, 5'b01111); + // Don't break concats.... + w5_u = {{0{1'b1}}, -4'sd7 }; + `checkh(w5_u, 5'b01001); + w9_s = { -4'sd7, -4'sd7 }; + `checkh(w9_s, 9'b010011001); + {w5_u, {w4_u}} = 9'b10101_1100; + `checkh(w5_u, 5'b10101); + `checkh(w4_u, 4'b1100); + {w4_u} = 4'b1011; + `checkh(w4_u, 4'b1011); + + if (fail) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_math_signed6.v b/test/cli/verilog/t_math_signed6.v new file mode 100644 index 00000000..3820a8b3 --- /dev/null +++ b/test/cli/verilog/t_math_signed6.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + + module t (/*AUTOARG*/); + + // signed source + logic signed [8-1:0] src; + + // destination structure + struct packed { + logic signed [16-1:0] s; + logic unsigned [16-1:0] u; + } dst; + + initial begin + // bug882 + // verilator lint_off WIDTH + src = 8'sh05; + dst = '{s: src, u: src}; + `checkh (dst.s, 16'h0005); + `checkh (dst.u, 16'h0005); + + src = 8'shf5; + dst = '{s: src, u: src}; + `checkh (dst.s, 16'hfff5); + `checkh (dst.u, 16'hfff5); + // verilator lint_on WIDTH + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_math_signed7.v b/test/cli/verilog/t_math_signed7.v new file mode 100644 index 00000000..0ed55b0b --- /dev/null +++ b/test/cli/verilog/t_math_signed7.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg alu_ltu, alu_lts; + logic [3:0] in_op1; + logic [3:0] in_op2; + + + reg aaa_ltu, aaa_lts; + always @(posedge clk) begin + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + aaa_ltu = in_op1 < in_op2; + // bug999 + aaa_lts = $signed(in_op1) < $signed(in_op2); + `checkh (aaa_ltu, 1'b0); + `checkh (aaa_lts, 1'b1); + end + + generate if (1) begin + always @(posedge clk) begin + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + alu_ltu = in_op1 < in_op2; + // bug999 + alu_lts = $signed(in_op1) < $signed(in_op2); + `checkh (alu_ltu, 1'b0); + `checkh (alu_lts, 1'b1); + $write("*-* All Finished *-*\n"); + $finish; + end + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_math_signed_wire.v b/test/cli/verilog/t_math_signed_wire.v new file mode 100644 index 00000000..0ddd9fa9 --- /dev/null +++ b/test/cli/verilog/t_math_signed_wire.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug511 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [7:0] au; + wire [7:0] as; + + Test1 test1 (.au); + Test2 test2 (.as); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] result=%x %x\n",$time, au, as); +`endif + if (au != 'h12) $stop; + if (as != 'h02) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test1 (output [7:0] au); + wire [7:0] b; + wire signed [3:0] c; + + // verilator lint_off WIDTH + assign c=-1; // 'hf + assign b=3; // 'h3 + assign au=b+c; // 'h12 + // verilator lint_on WIDTH +endmodule + + +module Test2 (output [7:0] as); + wire signed [7:0] b; + wire signed [3:0] c; + + // verilator lint_off WIDTH + assign c=-1; // 'hf + assign b=3; // 'h3 + assign as=b+c; // 'h12 + // verilator lint_on WIDTH +endmodule diff --git a/test/cli/verilog/t_math_strwidth.v b/test/cli/verilog/t_math_strwidth.v new file mode 100644 index 00000000..37a58925 --- /dev/null +++ b/test/cli/verilog/t_math_strwidth.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008-2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + reg [4*8:1] strg; + + initial begin + strg = "CHK"; + if (strg != "CHK") $stop; + if (strg == "JOE") $stop; + $write("String = %s = %x\n", strg, strg); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_math_svl2.v b/test/cli/verilog/t_math_svl2.v new file mode 100644 index 00000000..022f6291 --- /dev/null +++ b/test/cli/verilog/t_math_svl2.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + // New number format + if ('0 !== {66{1'b0}}) $stop; + if ('1 !== {66{1'b1}}) $stop; + if ('x !== {66{1'bx}}) $stop; + if ('z !== {66{1'bz}}) $stop; +`ifndef NC // NC-Verilog 5.50-s09 chokes on this test + if ("\v" != 8'd11) $stop; + if ("\f" != 8'd12) $stop; + if ("\a" != 8'd7) $stop; + if ("\x9a" != 8'h9a) $stop; + if ("\xf1" != 8'hf1) $stop; +`endif + end + if (cyc==8) begin + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_math_swap.v b/test/cli/verilog/t_math_swap.v new file mode 100644 index 00000000..f5a78c2f --- /dev/null +++ b/test/cli/verilog/t_math_swap.v @@ -0,0 +1,165 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] Operand1 = crc[31:0]; + wire [15:0] Operand2 = crc[47:32]; + wire Unsigned = crc[48]; + reg rst; + + parameter wl = 16; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [wl-1:0] Quotient; // From test of Test.v + wire [wl-1:0] Remainder; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .Quotient (Quotient[wl-1:0]), + .Remainder (Remainder[wl-1:0]), + // Inputs + .Operand1 (Operand1[wl*2-1:0]), + .Operand2 (Operand2[wl-1:0]), + .clk (clk), + .rst (rst), + .Unsigned (Unsigned)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, Quotient, Remainder}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h98d41f89a8be5693 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration); +`endif + cyc <= cyc + 1; + if (cyc < 20 || test.Iteration==4'd15) begin + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + end + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + rst <= 1'b1; + end + else if (cyc<20) begin + sum <= 64'h0; + rst <= 1'b0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'h8dd70a44972ad809) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); + + parameter wl = 16; + + input [wl*2-1:0] Operand1; + input [wl-1:0] Operand2; + input clk, rst, Unsigned; + output [wl-1:0] Quotient, Remainder; + + reg Cy, Overflow, Sign1, Sign2, Zero, Negative; + reg [wl-1:0] ah,al,Quotient, Remainder; + reg [3:0] Iteration; + reg [wl-1:0] sub_quot,op; + reg ah_ext; + + reg [1:0] a,b,c,d,e; + + always @(posedge clk) begin + if (!rst) begin + {a,b,c,d,e} = Operand1[9:0]; + {a,b,c,d,e} = {e,d,c,b,a}; + if (a != Operand1[1:0]) $stop; + if (b != Operand1[3:2]) $stop; + if (c != Operand1[5:4]) $stop; + if (d != Operand1[7:6]) $stop; + if (e != Operand1[9:8]) $stop; + end + end + + always @(posedge clk) begin + if (rst) begin + Iteration <= 0; + Quotient <= 0; + Remainder <= 0; + end + else begin + if (Iteration == 0) begin + {ah,al} = Operand1; + op = Operand2; + Cy = 0; + Overflow = 0; + Sign1 = (~Unsigned)&ah[wl-1]; + Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]); + if (Sign1) {ah,al} = -{ah,al}; + end +`define BUG1 +`ifdef BUG1 + {ah_ext,ah,al} = {ah,al,Cy}; +`else + ah_ext = ah[15]; + ah[15:1] = ah[14:0]; + ah[0] = al[15]; + al[15:1] = al[14:0]; + al[0] = Cy; +`endif +`ifdef TEST_VERBOSE + $display("%x %x %x %x %x %x %x %x %x", + Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); +`endif + {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; + if (Cy) + begin + {ah_ext,ah} = {1'b0,sub_quot}; + end + if (Iteration != 15 ) + begin + if (ah_ext) Overflow = 1; + end + else + begin + if (al[14] && ~Unsigned) Overflow = 1; + Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; + Remainder <= Sign1 ? -ah : ah; + if (Overflow) + begin + Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; + Remainder <= Unsigned ? 16'hffff : 16'h8000; + Zero = 1; + Negative = 1; + end + end + Iteration <= Iteration + 1; // Count number of times this instruction is repeated + end + end + +endmodule diff --git a/test/cli/verilog/t_math_tri.v b/test/cli/verilog/t_math_tri.v new file mode 100644 index 00000000..eb32a489 --- /dev/null +++ b/test/cli/verilog/t_math_tri.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + reg [3:0] a; + reg [99:0] x; + + initial begin + a = 4'b010x; + if (a[3:2] !== 2'b01) $stop; + if (|a !== 1'b1) $stop; + if (&a !== 1'b0) $stop; + x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_math_vliw.v b/test/cli/verilog/t_math_vliw.v new file mode 100644 index 00000000..bf6ab729 --- /dev/null +++ b/test/cli/verilog/t_math_vliw.v @@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [7:0] crc; + reg [223:0] sum; + + wire [255:0] mglehy = {32{~crc}}; + wire [215:0] drricx = {27{crc}}; + wire [15:0] apqrli = {2{~crc}}; + wire [2:0] szlfpf = crc[2:0]; + wire [15:0] dzosui = {2{crc}}; + wire [31:0] zndrba = {16{crc[1:0]}}; + wire [223:0] bxiouf; + + vliw vliw ( + // Outputs + .bxiouf (bxiouf), + // Inputs + .mglehy (mglehy[255:0]), + .drricx (drricx[215:0]), + .apqrli (apqrli[15:0]), + .szlfpf (szlfpf[2:0]), + .dzosui (dzosui[15:0]), + .zndrba (zndrba[31:0])); + + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==0) begin + // Setup + crc <= 8'hed; + sum <= 224'h0; + end + else if (cyc<90) begin + //$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf); + sum <= {sum[222:0],sum[223]} ^ bxiouf; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); + if (crc !== 8'b01110000) $stop; + if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module vliw ( + input[255:0] mglehy, + input[215:0] drricx, + input[15:0] apqrli, + input[2:0] szlfpf, + input[15:0] dzosui, + input[31:0] zndrba, + output wire [223:0] bxiouf + ); + + wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) + | ({29{apqrli}} & {mglehy[247:0], drricx}); + wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) + | ({21{dzosui}} & zhknfc[335:0]); + wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; + wire [223:0] rzyeut = viuvoc[335:112]; + assign bxiouf = {rzyeut[7:0], + rzyeut[15:8], + rzyeut[23:16], + rzyeut[31:24], + rzyeut[39:32], + rzyeut[47:40], + rzyeut[55:48], + rzyeut[63:56], + rzyeut[71:64], + rzyeut[79:72], + rzyeut[87:80], + rzyeut[95:88], + rzyeut[103:96], + rzyeut[111:104], + rzyeut[119:112], + rzyeut[127:120], + rzyeut[135:128], + rzyeut[143:136], + rzyeut[151:144], + rzyeut[159:152], + rzyeut[167:160], + rzyeut[175:168], + rzyeut[183:176], + rzyeut[191:184], + rzyeut[199:192], + rzyeut[207:200], + rzyeut[215:208], + rzyeut[223:216]}; + +endmodule diff --git a/test/cli/verilog/t_math_width.v b/test/cli/verilog/t_math_width.v new file mode 100644 index 00000000..a9ba1878 --- /dev/null +++ b/test/cli/verilog/t_math_width.v @@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (); + + // See also t_lint_width + + parameter A_ONE = '1; + // verilator lint_off WIDTH + parameter [3:0] A_W4 = A_ONE; + // verilator lint_on WIDTH + initial begin + if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; + if ($bits(A_W4) != 4) $stop; + if (A_W4 != 4'b0001) $stop; + end + + b #(.B_WIDTH(48)) b (); + + reg [4:0] c; + integer c_i; + initial begin + c_i = 3; + c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax + if (c != 5'b1000) $stop; + end + + localparam D_TT = 32'd23; + localparam D_SIX = 6; + // verilator lint_off WIDTH + localparam [5:0] D_SUB = D_TT - D_SIX; + // verilator lint_on WIDTH + initial begin + if (D_SUB != 17) $stop; + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + + +module b; + parameter B_WIDTH = 1; + localparam B_VALUE0 = {B_WIDTH{1'b0}}; + localparam B_VALUE1 = {B_WIDTH{1'b1}}; + reg [47:0] b_val; + initial begin + b_val = B_VALUE0; + if (b_val != 48'b0) $stop; + b_val = B_VALUE1; + if (b_val != ~48'b0) $stop; + end +endmodule diff --git a/test/cli/verilog/t_math_yosys.v b/test/cli/verilog/t_math_yosys.v new file mode 100644 index 00000000..9fe06d07 --- /dev/null +++ b/test/cli/verilog/t_math_yosys.v @@ -0,0 +1,84 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 Claire Wolf. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] y1; // From d1 of demo_001.v + wire [7:0] y2; // From d1 of demo_001.v + wire [7:0] y3; // From d1 of demo_001.v + wire [7:0] y4; // From d1 of demo_001.v + wire [31:0] z0; // From d2 of demo_002.v + wire [31:0] z1; // From d2 of demo_002.v + wire [31:0] z2; // From d2 of demo_002.v + wire [31:0] z3; // From d2 of demo_002.v + // End of automatics + + demo_001 d1(/*AUTOINST*/ + // Outputs + .y1 (y1[7:0]), + .y2 (y2[7:0]), + .y3 (y3[7:0]), + .y4 (y4[7:0])); + demo_002 d2(/*AUTOINST*/ + // Outputs + .z0 (z0[31:0]), + .z1 (z1[31:0]), + .z2 (z2[31:0]), + .z3 (z3[31:0])); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (y1 !== 8'h7b) $stop; + if (y2 !== 8'h7c) $stop; + if (y3 !== 8'h7b) $stop; + if (y4 !== 8'h7c) $stop; + if (z0 !== 32'h00000000) $stop; + if (z1 !== 32'hffffffff) $stop; + if (z2 !== 32'hffffffff) $stop; + if (z3 !== 32'hffffffff) $stop; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module demo_001(y1, y2, y3, y4); + output [7:0] y1, y2, y3, y4; + + // verilator lint_off REALCVT + localparam [7:0] p1 = 123.45; + localparam real p2 = 123.45; + localparam real p3 = 123; + localparam p4 = 123.45; + + // verilator lint_off WIDTH + assign y1 = p1 + 0.2; + assign y2 = p2 + 0.2; + assign y3 = p3 + 0.2; + assign y4 = p4 + 0.2; + // verilator lint_on WIDTH +endmodule + +module demo_002(z0, z1, z2, z3); + output [31:0] z0, z1, z2, z3; + + // verilator lint_off WIDTH + assign z0 = 1'bx >= (-1 * -1.17); + // verilator lint_on WIDTH + assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0; + assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0; + assign z3 = 1 ? -1 : 'd0; +endmodule diff --git a/test/cli/verilog/t_mem_banks.v b/test/cli/verilog/t_mem_banks.v new file mode 100644 index 00000000..b810ca53 --- /dev/null +++ b/test/cli/verilog/t_mem_banks.v @@ -0,0 +1,73 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + reg [5:0] addr; + + parameter BANKS = 6; + parameter ROWS = 8; + + wire [2:0] bank; + wire [2:0] row; + + integer a; + integer used[BANKS][ROWS]; + + // Test loop + initial begin + for (a = 0; a < BANKS*ROWS; ++a) begin + addr[5:0] = a[5:0]; + hash (addr, bank, row); + used [bank][row] ++; + if (used [bank][row] > 1) begin + $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); + end + end + $write("*-* All Finished *-*\n"); + $finish; + end + + task hash (input [5:0] addr, + output [2:0] bank, + output [2:0] row); + + reg [1:0] third; + reg [1:0] fourth; + + third = {addr[5], addr[4]}; + fourth = {addr[3] ^ addr[1], + addr[2] ^ addr[0]}; + + case (third) + 2'h0: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end + 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end + endcase + + 2'h1: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end + endcase + + 2'h2: + case (fourth) + 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end + endcase + + 2'h3: $stop; + endcase + endtask +endmodule diff --git a/test/cli/verilog/t_mem_cond.v b/test/cli/verilog/t_mem_cond.v new file mode 100644 index 00000000..b5d6f3f6 --- /dev/null +++ b/test/cli/verilog/t_mem_cond.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + b, + // Inputs + clk, en, a + ); + + // bug1017 + + input clk; + + input en; + input a[1]; + output logic b[1]; + + always_ff @ (posedge clk) begin + b <= en ? a : b; + end + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_mem_fifo.v b/test/cli/verilog/t_mem_fifo.v new file mode 100644 index 00000000..8702c496 --- /dev/null +++ b/test/cli/verilog/t_mem_fifo.v @@ -0,0 +1,111 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + + wire [65:0] outData; // From fifo of fifo.v + wire [15:0] inData = crc[15:0]; + wire [1:0] inWordPtr = crc[17:16]; + wire wrEn = crc[20]; + wire [1:0] wrPtr = crc[33:32]; + wire [1:0] rdPtr = crc[34:33]; + + fifo fifo ( + // Outputs + .outData (outData[65:0]), + // Inputs + .clk (clk), + .inWordPtr (inWordPtr[1:0]), + .inData (inData[15:0]), + .rdPtr (rdPtr), + .wrPtr (wrPtr), + .wrEn (wrEn)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc==90) begin + if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; + end + else if (cyc==91) begin + if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; + end + else if (cyc==92) begin + if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; + end + else if (cyc==93) begin + if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; + end + else if (cyc==94) begin + if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module fifo (/*AUTOARG*/ + // Outputs + outData, + // Inputs + clk, inWordPtr, inData, wrPtr, rdPtr, wrEn + ); + + parameter fifoDepthLog2 = 1; + parameter fifoDepth = 1<10 && cyc<90) begin + sum <= {sum[30:0],sum[31]} ^ {out1, out0}; + end + else if (cyc==99) begin + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module fifo (/*AUTOARG*/ + // Outputs + out0, out1, + // Inputs + clk, wr0a, wr0b, wr1a, wr1b, inData + ); + + input clk; + input wr0a; + input wr0b; + input wr1a; + input wr1b; + input [15:0] inData; + + output [15:0] out0; + output [15:0] out1; + + reg [15:0] mem [1:0]; + reg [15:0] memtemp2 [1:0]; + reg [15:0] memtemp3 [1:0]; + + assign out0 = {mem[0] ^ memtemp2[0]}; + assign out1 = {mem[1] ^ memtemp3[1]}; + + always @(posedge clk) begin + // These mem assignments must be done in order after processing + if (wr0a) begin + memtemp2[0] <= inData; + mem[0] <= inData; + end + if (wr0b) begin + memtemp3[0] <= inData; + mem[0] <= ~inData; + end + if (wr1a) begin + memtemp3[1] <= inData; + mem[1] <= inData; + end + if (wr1b) begin + memtemp2[1] <= inData; + mem[1] <= ~inData; + end + end + +endmodule diff --git a/test/cli/verilog/t_mem_multi_io.v b/test/cli/verilog/t_mem_multi_io.v new file mode 100644 index 00000000..e94b9860 --- /dev/null +++ b/test/cli/verilog/t_mem_multi_io.v @@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic [7:0] arr [7:0]; + logic [7:0] arri [7:0]; + + has_array am1 (.clk(clk), .arri(arr), .arro(arri)); + + integer cyc; initial cyc = 0; + + initial begin + for (int i = 0; i < 8; i++) begin + arr[i] = 0; + end + end + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5 && arri[1] != 8) begin + $stop; + end + for (int i = 0; i < 7; ++i) begin + arr[i+1] <= arr[i]; + end + arr[0] <= arr[0] + 1; + end + +endmodule : t + +module has_array ( + input clk, + input logic [7:0] arri [7:0], + output logic [7:0] arro [7:0] + ); + + integer cyc; initial cyc = 0; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (arri[0] == 10 && cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always @(posedge clk) begin + for (integer i = 0; i < 7; ++i) begin + arro[i+1] <= arro[i]; + end + arro[0] = arro[0] + 2; + end + +endmodule : has_array diff --git a/test/cli/verilog/t_mem_multi_io2.v b/test/cli/verilog/t_mem_multi_io2.v new file mode 100644 index 00000000..d43e65d2 --- /dev/null +++ b/test/cli/verilog/t_mem_multi_io2.v @@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + o3, o34, o345, + // Inputs + i3, i34, i345 + ); + input [15:0] i3; + output wire [15:0] o3; + input [15:0] i34 [3:0]; + output wire [15:0] o34 [3:0]; + input [15:0] i345 [3:0][4:0]; + output wire [15:0] o345 [3:0][4:0]; + + sub sub (.*); +endmodule + +module sub (/*AUTOARG*/ + // Outputs + o3, o34, o345, + // Inputs + i3, i34, i345 + ); + input [15:0] i3; + output wire [15:0] o3; + input [15:0] i34 [3:0]; + output wire [15:0] o34 [3:0]; + input [15:0] i345 [3:0][4:0]; + output wire [15:0] o345 [3:0][4:0]; + + assign o3 = i3; + assign o34 = i34; + assign o345 = i345; + +endmodule diff --git a/test/cli/verilog/t_mem_multidim.v b/test/cli/verilog/t_mem_multidim.v new file mode 100644 index 00000000..cee7bcd2 --- /dev/null +++ b/test/cli/verilog/t_mem_multidim.v @@ -0,0 +1,100 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off LITENDIAN + // verilator lint_off BLKANDNBLK + // 3 3 4 + reg [71:0] memw [2:0][1:3][5:2]; + reg [7:0] memn [2:0][1:3][5:2]; + // verilator lint_on BLKANDNBLK + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [71:0] wide; + reg [7:0] narrow; + reg [1:0] index0; + reg [1:0] index1; + reg [2:0] index2; + integer i0,i1,i2; + + integer imem[2:0][1:3]; + reg [2:0] cstyle[2]; + // verilator lint_on LITENDIAN + + initial begin + for (i0=0; i0<3; i0=i0+1) begin + for (i1=1; i1<4; i1=i1+1) begin + imem[i0[1:0]] [i1[1:0]] = i1; + for (i2=2; i2<6; i2=i2+1) begin + memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; + memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; + end + end + end + end + + reg [71:0] wread; + reg wreadb; + + always @ (posedge clk) begin + //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + narrow <= 8'h0; + wide <= 72'h0; + index0 <= 2'b0; + index1 <= 2'b0; + index2 <= 3'b0; + end + else if (cyc<90) begin + index0 <= crc[1:0]; + index1 <= crc[3:2]; + index2 <= crc[6:4]; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + + // We never read past bounds, or get unspecific results + // We also never read lowest indexes, as writing outside of range may corrupt them + if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin + narrow <= ({narrow[6:0], narrow[7]^narrow[0]} + ^ {memn[index0][index1][index2]}); + wread = memw[index0][index1][index2]; + wreadb = memw[index0][index1][index2][2]; + wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); + //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); + end + // We may write past bounds of memory + memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; + memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; + memw[index0][index1][index2] <= {~crc[7:0],crc}; + //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); + cstyle[cyc[0]] <= cyc[2:0]; + if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; + end + else if (cyc==90) begin + memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; + end + else if (cyc==91) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide); + if (crc != 64'h65e3bddcd9bc2750) $stop; + if (narrow != 8'hca) $stop; + if (wide != 72'h4edafed31ba6873f73) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_mem_packed.v b/test/cli/verilog/t_mem_packed.v new file mode 100644 index 00000000..52a38bf9 --- /dev/null +++ b/test/cli/verilog/t_mem_packed.v @@ -0,0 +1,180 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + //Simple debug: + //wire [1:1] wir_a [3:3] [2:2]; //11 + //logic [1:1] log_a [3:3] [2:2]; //12 + //wire [3:3] [2:2] [1:1] wir_p; //13 + //logic [3:3] [2:2] [1:1] log_p; //14 + + integer cyc; initial cyc = 0; +`ifdef IVERILOG + reg [7:0] arr [3:0]; + wire [7:0] arr_w [3:0]; +`else + reg [3:0] [7:0] arr; + wire [3:0] [7:0] arr_w; +`endif + reg [7:0] sum; + reg [7:0] sum_w; + integer i0; + + initial begin + for (i0=0; i0<5; i0=i0+1) begin + arr[i0] = 1 << (i0[1:0]*2); + end + end + + assign arr_w = arr; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + sum <= 0; + sum_w <= 0; + end + else if (cyc >= 10 && cyc < 14) begin + sum <= sum + arr[cyc-10]; + + sum_w <= sum_w + arr_w[cyc-10]; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum); + if (sum != 8'h55) $stop; + if (sum != sum_w) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // Test ordering of packed dimensions + logic [31:0] data_out; + logic [31:0] data_out2; + logic [0:0] [2:0] [31:0] data_in; + logic [31:0] data_in2 [0:0] [2:0]; + assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; + assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; + + logic [31:0] last_data_out; + always @ (posedge clk) begin + if (cyc <= 2) begin + data_in[0][0] <= 0; + data_in[0][1] <= 0; + data_in[0][2] <= 0; + data_in2[0][0] <= 0; + data_in2[0][1] <= 0; + data_in2[0][2] <= 0; + end + else if (cyc > 2 && cyc < 99) begin + data_in[0][0] <= data_in[0][0] + 1; + data_in[0][1] <= data_in[0][1] + 1; + data_in[0][2] <= data_in[0][2] + 1; + data_in2[0][0] <= data_in2[0][0] + 1; + data_in2[0][1] <= data_in2[0][1] + 1; + data_in2[0][2] <= data_in2[0][2] + 1; + last_data_out <= data_out; +`ifdef TEST_VERBOSE + $write("data_out %0x %0x\n", data_out, last_data_out); +`endif + if (cyc > 4 && data_out != last_data_out + 3) $stop; + if (cyc > 4 && data_out != data_out2) $stop; + end + end + + // Test for mixed implicit/explicit dimensions and all implicit packed + bit [3:0][7:0][1:0] vld [1:0][1:0]; + bit [3:0][7:0][1:0] vld2; + + // There are specific nodes for Or, Xor, Xnor and And + logic vld_or; + logic vld2_or; + assign vld_or = |vld[0][0]; + assign vld2_or = |vld2; + + logic vld_xor; + logic vld2_xor; + assign vld_xor = ^vld[0][0]; + assign vld2_xor = ^vld2; + + logic vld_xnor; + logic vld2_xnor; + assign vld_xnor = ~^vld[0][0]; + assign vld2_xnor = ~^vld2; + + logic vld_and; + logic vld2_and; + assign vld_and = &vld[0][0]; + assign vld2_and = &vld2; + + // Bit reductions should be cloned, other unary operations should clone the + // entire assign. + bit [3:0][7:0][1:0] not_lhs; + bit [3:0][7:0][1:0] not_rhs; + assign not_lhs = ~not_rhs; + + // Test an AstNodeUniop that shouldn't be expanded + bit [3:0][7:0][1:0] vld2_inv; + assign vld2_inv = ~vld2; + + initial begin + for (int i=0; i<4; i=i+2) begin + for (int j=0; j<8; j=j+2) begin + vld[0][0][i][j] = 2'b00; + vld[0][0][i+1][j+1] = 2'b00; + vld2[i][j] = 2'b00; + vld2[i+1][j+1] = 2'b00; + not_rhs[i][j] = i[1:0]; + not_rhs[i+1][j+1] = i[1:0]; + end + end + end + + + logic [3:0] expect_cyc; initial expect_cyc = 'd15; + + always @(posedge clk) begin + expect_cyc <= expect_cyc + 1; + for (int i=0; i<4; i=i+1) begin + for (int j=0; j<8; j=j+1) begin + vld[0][0][i][j] <= vld[0][0][i][j] + 1; + vld2[i][j] <= vld2[i][j] + 1; + if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; + not_rhs[i][j] <= not_rhs[i][j] + 1; + end + end + if (cyc % 8 == 0) begin + vld[0][0][0][0] <= vld[0][0][0][0] - 1; + vld2[0][0] <= vld2[0][0] - 1; + end + if (expect_cyc < 8 && !vld_xor) $stop; + else if (expect_cyc > 7 && vld_xor) $stop; + + if (expect_cyc < 8 && vld_xnor) $stop; + else if (expect_cyc > 7 && !vld_xnor) $stop; + + if (expect_cyc == 15 && vld_or) $stop; + else if (expect_cyc == 11 && vld_or) $stop; + else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; + + if (expect_cyc == 10 && !vld_and) $stop; + else if (expect_cyc == 14 && !vld_and) $stop; + else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; + + if (vld_xor != vld2_xor) $stop; + if (vld_xnor != vld2_xnor) $stop; + if (vld_or != vld2_or) $stop; + if (vld_and != vld2_and) $stop; + end + +endmodule diff --git a/test/cli/verilog/t_mem_packed_assign.v b/test/cli/verilog/t_mem_packed_assign.v new file mode 100644 index 00000000..98e5c911 --- /dev/null +++ b/test/cli/verilog/t_mem_packed_assign.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + /* verilator lint_off WIDTH */ + + input clk; + + integer cyc; initial cyc = 0; + logic [31:0] arr_c; initial arr_c = 0; + logic [7:0] [3:0] arr; + + logic [31:0] arr2_c; initial arr2_c = 0; + logic [7:0] [3:0] arr2; + assign arr2_c = arr2; + + always @ (posedge clk) begin + cyc <= cyc + 1; + arr_c <= arr_c + 1; + arr2 <= arr2 + 1; +`ifdef TEST_VERBOSE + $write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], arr[3]); +`endif + if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + /* verilator lint_on WIDTH */ + +endmodule diff --git a/test/cli/verilog/t_mem_shift.v b/test/cli/verilog/t_mem_shift.v new file mode 100644 index 00000000..9302f09e --- /dev/null +++ b/test/cli/verilog/t_mem_shift.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + + integer i; + reg [63:0] mem [7:0]; + + always @ (posedge clk) begin + if (cyc==1) begin + for (i=0; i<8; i=i+1) begin + mem[i] <= 64'h0; + end + end + else begin + mem[0] <= crc; + for (i=1; i<8; i=i+1) begin + mem[i] <= mem[i-1]; + end + end + end + + wire [63:0] outData = mem[7]; + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc==90) begin + if (outData != 64'h1265e3bddcd9bc27) $stop; + end + else if (cyc==91) begin + if (outData != 64'h24cbc77bb9b3784e) $stop; + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_mem_slice.v b/test/cli/verilog/t_mem_slice.v new file mode 100644 index 00000000..fe084c1e --- /dev/null +++ b/test/cli/verilog/t_mem_slice.v @@ -0,0 +1,124 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic use_AnB; + logic [1:0] active_command [8:0]; + logic [1:0] command_A [8:0]; + logic [1:0] command_B [8:0]; + + logic [1:0] active_command2 [8:0]; + logic [1:0] command_A2 [8:0]; + logic [1:0] command_B2 [8:0]; + + logic [1:0] active_command3 [1:0][2:0][3:0]; + logic [1:0] command_A3 [1:0][2:0][3:0]; + logic [1:0] command_B3 [1:0][2:0][3:0]; + + logic [2:0] use_A4nB4; + logic [8:0][1:0] active_command4; + logic [8:0][1:0] command_A4; + logic [8:0][1:0] command_B4; + + logic [8:0] pipe1 [7:0]; + logic [8:0] pipe1_input; + + integer cyc; + + assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; + assign active_command2 = (use_AnB) ? command_A2 : command_B2; + // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing + assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; + + // Check we can cope with things other than packed arrays + assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; + + always @ (posedge clk) begin + pipe1_input <= pipe1_input + 1; + pipe1[0] <= pipe1_input; + pipe1[7:1] <= pipe1[6:0]; + end + + logic [3:0][13:0] iq_read_data [15:0]; + logic [3:0][13:0] iq_data; + logic [3:0] sel; + + assign iq_data = iq_read_data[sel]; + + always @ (posedge clk) begin + sel = sel + 1; + end + + initial begin + cyc = 0; + use_AnB = 0; + for (int i = 0; i < 7; ++i) begin + command_A[i] = 2'b00; + command_B[i] = 2'b11; + command_A2[i] = 2'b00; + command_B2[i] = 2'b11; + pipe1_input = 9'b0; + end + for (int i = 0; i < 2; ++i) begin + for (int j = 0; j < 3; ++j) begin + for (int k = 0; k < 4; ++k) begin + command_A3[i][j][k] = 2'b00; + command_B3[i][j][k] = 2'b11; + end + end + end + end + + always @ (posedge clk) begin + use_AnB <= ~use_AnB; + cyc <= cyc + 1; + if (use_AnB) begin + if (active_command[3] != 2'b00) begin + $stop; + end + if (active_command2[3] != 2'b00) begin + $stop; + end + if (active_command3[0][1][2] != 2'b00) begin + $stop; + end + end + if (!use_AnB) begin + if (active_command[3] != 2'b11) begin + $stop; + end + if (active_command2[3] != 2'b11) begin + $stop; + end + end + end + + logic [8:0] last_pipe; + always @(posedge clk) begin + if (cyc < 3) begin + last_pipe <= pipe1[0]; + end + else begin + if (last_pipe + 1 != pipe1[0]) begin + $stop; + end + else begin + last_pipe <= pipe1[0]; + end + end + if (cyc > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule : t diff --git a/test/cli/verilog/t_mem_slot.v b/test/cli/verilog/t_mem_slot.v new file mode 100644 index 00000000..9c03ffac --- /dev/null +++ b/test/cli/verilog/t_mem_slot.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define RegDel 1 + +module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); + + input Clk; + input [1:0] SlotIdx; + input BitToChange; + input BitVal; + input [1:0] SlotToReturn; + output reg [1:0] OutputVal; + + reg [1:0] Array[2:0]; + + always @(posedge Clk) + begin + Array[SlotIdx][BitToChange] <= #`RegDel BitVal; + + OutputVal = Array[SlotToReturn]; + end +endmodule diff --git a/test/cli/verilog/t_mem_twoedge.v b/test/cli/verilog/t_mem_twoedge.v new file mode 100644 index 00000000..9c241853 --- /dev/null +++ b/test/cli/verilog/t_mem_twoedge.v @@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // verilator lint_off MULTIDRIVEN + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + wire [15:0] out2; // From test of Test.v + // End of automatics + // verilator lint_on MULTIDRIVEN + + Test test ( + .en (crc[21:20]), + .a1 (crc[19:18]), + .a0 (crc[17:16]), + .d1 (crc[15:8]), + .d0 (crc[7:0]), + /*AUTOINST*/ + // Outputs + .out (out[31:0]), + .out2 (out2[15:0]), + // Inputs + .clk (clk)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out2, 16'h0, out}; + + // Test loop +`ifdef TEST_VERBOSE + always @ (negedge clk) begin + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); + end +`endif + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + test.clear(); + end + else if (cyc<10) begin + sum <= 64'h0; + test.clear(); + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc68a94a34ec970aa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, out2, + // Inputs + clk, en, a0, a1, d0, d1 + ); + + input clk; + input [1:0] en; + input [1:0] a0; + input [1:0] a1; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + // verilator lint_off MULTIDRIVEN + output reg [15:0] out2; + + reg [7:0] mem [4]; + // verilator lint_on MULTIDRIVEN + + task clear(); + for (int i=0; i<4; ++i) mem[i] = 0; + endtask + + always @(posedge clk) begin + if (en[0]) begin + mem[a0] <= d0; + out2[7:0] <= d0; + end + end + always @(negedge clk) begin + if (en[1]) begin + mem[a1] <= d1; + out2[15:8] <= d0; + end + end + + assign out = {mem[3],mem[2],mem[1],mem[0]}; + +endmodule diff --git a/test/cli/verilog/t_mod_dup_ign.v b/test/cli/verilog/t_mod_dup_ign.v new file mode 100644 index 00000000..8b06b445 --- /dev/null +++ b/test/cli/verilog/t_mod_dup_ign.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + sub sub (); +endmodule + +module sub; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +// verilator lint_off MODDUP +module sub; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_mod_interface_array0.v b/test/cli/verilog/t_mod_interface_array0.v new file mode 100644 index 00000000..00c600b9 --- /dev/null +++ b/test/cli/verilog/t_mod_interface_array0.v @@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 + +parameter N = 4; + +interface a_if #(parameter PARAM = 0) (); + logic long_name; + modport source (output long_name); + modport sink (input long_name); +endinterface + +module intf_source + ( + input logic [N-1:0] intf_input, + a_if.source i_intf_source[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate +endmodule + +module intf_sink + ( + output [N-1:0] a_out, + a_if.sink i_intf_sink[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate +endmodule + +module t + ( + clk + ); + input clk; + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + a_if #(.PARAM(1)) tl_intf [N-1:0] (); + intf_source source(a_in, tl_intf); + intf_sink sink(a_out, tl_intf); + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_mod_interface_array1.v b/test/cli/verilog/t_mod_interface_array1.v new file mode 100644 index 00000000..f524a79a --- /dev/null +++ b/test/cli/verilog/t_mod_interface_array1.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 + +parameter N = 4; + +interface a_if #(parameter PARAM = 0) (); + logic long_name; + modport source (output long_name); + modport sink (input long_name); +endinterface + +module intf_source + ( + input logic [N-1:0] intf_input, + a_if.source i_intf_source[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate +endmodule + +module intf_sink + ( + output [N-1:0] a_out, + a_if.sink i_intf_sink[N-1:0] + ); + generate + for (genvar i=0; i < N;i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate +endmodule + +module t + ( + clk + ); + input clk; + logic [N-1:0] a_in; + logic [N-1:0] a_out; + logic [N-1:0] ack_out; + // verilator lint_off LITENDIAN + a_if #(.PARAM(1)) tl_intf [N] (); + // verilator lint_on LITENDIAN + intf_source source(a_in, tl_intf); + intf_sink sink(a_out, tl_intf); + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_mod_interface_array2.v b/test/cli/verilog/t_mod_interface_array2.v new file mode 100644 index 00000000..0c8101c6 --- /dev/null +++ b/test/cli/verilog/t_mod_interface_array2.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 + +parameter N = 4; +// verilator lint_off LITENDIAN + +interface a_if #(parameter PARAM = 0) (); + logic long_name; + modport source (output long_name); + modport sink (input long_name); +endinterface + +module intf_source + ( + input logic [0:N-1] intf_input, + a_if.source i_intf_source[0:N-1] + ); + generate + for (genvar i=0; i < N;i++) begin + assign i_intf_source[i].long_name = intf_input[i]; + end + endgenerate +endmodule + +module intf_sink + ( + output [0:N-1] a_out, + a_if.sink i_intf_sink[0:N-1] + ); + generate + for (genvar i=0; i < N;i++) begin + assign a_out[i] = i_intf_sink[i].long_name; + end + endgenerate +endmodule + +module t + ( + clk + ); + input clk; + logic [0:N-1] a_in; + logic [0:N-1] a_out; + logic [0:N-1] ack_out; + a_if #(.PARAM(1)) tl_intf [0:N-1] (); + intf_source source(a_in, tl_intf); + intf_sink sink(a_out, tl_intf); + + initial a_in = '0; + always @(posedge clk) begin + a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; + ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; + if (ack_out != a_out) begin + $stop; + end + + if (& a_in) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_mod_recurse1.v b/test/cli/verilog/t_mod_recurse1.v new file mode 100644 index 00000000..785e3886 --- /dev/null +++ b/test/cli/verilog/t_mod_recurse1.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Sean Moore. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + rec rec (); + +endmodule + +module rec; + parameter DEPTH = 1; + + generate + if (DEPTH==1) begin + rec #(.DEPTH(DEPTH+1)) sub; + end + else if (DEPTH==2) begin + rec #(.DEPTH(DEPTH+1)) subb; + end + else if (DEPTH==3) begin + bottom #(.DEPTH(DEPTH+1)) bot; + end + endgenerate +endmodule + +module bottom; + parameter DEPTH = 1; + initial begin + if (DEPTH!=4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_mod_uselib.v b/test/cli/verilog/t_mod_uselib.v new file mode 100644 index 00000000..f51299a0 --- /dev/null +++ b/test/cli/verilog/t_mod_uselib.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); +// // `uselib {dir= | file= | libext= | lib= +`uselib libext=.v + s s (); +endmodule + +module s; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_multitop1s.v b/test/cli/verilog/t_multitop1s.v new file mode 100644 index 00000000..34282dd6 --- /dev/null +++ b/test/cli/verilog/t_multitop1s.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t_multitop1s; + initial $display("In '%m'"); +endmodule + +module in_subfile; + initial $display("In '%m'"); +endmodule diff --git a/test/cli/verilog/t_multitop_sig.v b/test/cli/verilog/t_multitop_sig.v new file mode 100644 index 00000000..4f1d3433 --- /dev/null +++ b/test/cli/verilog/t_multitop_sig.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module a(in, out); + input in; + output out; + assign out = !in; + sub sub (); + initial $display("In '%m'"); +endmodule + +module b(in, out); + input in; + output out; + assign out = in; + sub sub (); + initial $display("In '%m'"); +endmodule + +module c(uniq_in, uniq_out); + input uniq_in; + output uniq_out; + assign uniq_out = !uniq_in; + sub sub (); + initial $display("In '%m'"); +endmodule + +module sub; + initial $display("In '%m'"); +endmodule diff --git a/test/cli/verilog/t_no_sel_assign_merge_in_cpp.v b/test/cli/verilog/t_no_sel_assign_merge_in_cpp.v new file mode 100644 index 00000000..6c7f1a62 --- /dev/null +++ b/test/cli/verilog/t_no_sel_assign_merge_in_cpp.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t_no_sel_assign_merge_in_cpp ( + input wire [(8*39)-1:0] d_i, + output wire [(8*32)-1:0] d_o +); + for (genvar i = 0; i < 8; i = i + 1) begin + assign d_o[i*32 +: 32] = d_i[i*39 +: 32]; + end +endmodule diff --git a/test/cli/verilog/t_opt_table_enum.v b/test/cli/verilog/t_opt_table_enum.v new file mode 100644 index 00000000..538cf3be --- /dev/null +++ b/test/cli/verilog/t_opt_table_enum.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + enum { + CASE_0 = 0, + CASE_1 = 1, + CASE_2 = 2, + CASE_4 = 4, + CASE_5 = 5, + DEFAULT = 99 + } e; + + reg [2:0] cyc; + + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + always @* begin + case (cyc) + 3'b000: e = CASE_0; + 3'b001: e = CASE_1; + 3'b010: e = CASE_2; + 3'b100: e = CASE_4; + 3'b101: e = CASE_5; + default: e = DEFAULT; + endcase + end + + always @(posedge clk) begin + $display("cyle %d = %d", cyc, e); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_opt_table_packed_array.v b/test/cli/verilog/t_opt_table_packed_array.v new file mode 100644 index 00000000..9cd2d550 --- /dev/null +++ b/test/cli/verilog/t_opt_table_packed_array.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + logic [3:0][3:0] a; + + reg [2:0] cyc; + + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + always @* begin + case (cyc) + 3'b000: a = {4'd0, 4'd1, 4'd2, 4'd3}; + 3'b001: a = {4'd1, 4'd2, 4'd3, 4'd4}; + 3'b010: a = {4'd4, 4'd3, 4'd4, 4'd5}; + 3'b100: a = {4'd4, 4'd5, 4'd6, 4'd7}; + 3'b101: a = {4'd5, 4'd6, 4'd7, 4'd8}; + default: a = {4{4'hf}}; + endcase + end + + always @(posedge clk) begin + $display("cyle %d = { %d, %d, %d, %d }", cyc, a[0], a[1], a[2], a[3]); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_opt_table_same.v b/test/cli/verilog/t_opt_table_same.v new file mode 100644 index 00000000..c2317dce --- /dev/null +++ b/test/cli/verilog/t_opt_table_same.v @@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int i; + int j; + + reg [2:0] cyc; + + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + always @* begin + case (cyc) + 3'b000: i = 0; + 3'b001: i = 1; + 3'b010: i = 2; + 3'b100: i = 4; + 3'b101: i = 5; + default: i = 99; + endcase + end + + // Equivalent to above + always @* begin + case (cyc) + 3'b101: j = 5; + 3'b100: j = 4; + 3'b010: j = 2; + 3'b001: j = 1; + 3'b000: j = 0; + default: j = 99; + endcase + end + + always @(posedge clk) begin + $display("cyle %d = %d %d", cyc, i, j); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_opt_table_signed.v b/test/cli/verilog/t_opt_table_signed.v new file mode 100644 index 00000000..8dbd80a9 --- /dev/null +++ b/test/cli/verilog/t_opt_table_signed.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int i; + + reg [2:0] cyc; + + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + always @* begin + case (cyc) + 3'b000: i = 0; + 3'b001: i = -1; + 3'b010: i = 2; + 3'b100: i = -4; + 3'b101: i = 5; + default: i = -1 << 31; + endcase + end + + always @(posedge clk) begin + $display("cyle %d = %d", cyc, i); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_opt_table_sparse.v b/test/cli/verilog/t_opt_table_sparse.v new file mode 100644 index 00000000..3145d3c1 --- /dev/null +++ b/test/cli/verilog/t_opt_table_sparse.v @@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int i; + + reg [2:0] cyc; + + initial cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + /* verilator lint_off LATCH */ + always @* begin + case (cyc) + 3'b000: i = 0; + 3'b001: i = 1; + 3'b010: ; // unset + 3'b100: i = 4; + 3'b101: i = 5; + default: i = 99; + endcase + end + /* verilator lint_on LATCH */ + + always @(posedge clk) begin + $display("cyle %d = %d", cyc, i); + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_optm_if_array.v b/test/cli/verilog/t_optm_if_array.v new file mode 100644 index 00000000..5be6aae1 --- /dev/null +++ b/test/cli/verilog/t_optm_if_array.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + dinitout, + // Inputs + clk, rstn + ); + + input clk; + input rstn; + output [31:0] dinitout; + + wire zero; + assign zero = 1'd0; + + reg [31:0] dinit [0:1]; + wire [31:0] dinitout = dinit[0] | dinit[1]; + + reg rstn_r; // .pl file checks that this signal gets optimized away + always @(posedge clk) begin + rstn_r <= rstn; + end + + always @(posedge clk) begin + if ((rstn_r == 0)) begin // Will optimize away + dinit[0] <= '0; + end + else begin + dinit[0] <= {31'd0, zero}; + end + end + + always @(posedge clk) begin + if ((rstn_r == 0)) begin // Will optimize away + dinit[1] <= 1234; + end + else begin + dinit[1] <= 1234; + end + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_optm_if_cond.v b/test/cli/verilog/t_optm_if_cond.v new file mode 100644 index 00000000..f9509efa --- /dev/null +++ b/test/cli/verilog/t_optm_if_cond.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Outputs + q0, q1, q2, q3, q4, + // Inputs + clk, rst, en, i0, i1, i2, i3, i4 + ); + input clk; + + input rst; + input en; + output int q0; input int i0; + output int q1; input int i1; + output int q2; input int i2; + output int q3; input int i3; + output int q4; input int i4; + + always @ (posedge clk) begin + if (rst) begin + if (en) q0 <= i0; + end + else q0 <= 0; + + if (rst) begin + if (en) q1 <= i1; + end + else q1 <= 0; + + if (rst) begin + if (en) q2 <= i2; + end + else q2 <= 0; + + if (rst) begin + if (en) q3 <= i3; + end + else q3 <= 0; + end + + always_comb begin + q4 = i4; + if (q4 == 0) begin + // Conflicts with condition + q4 = 1; + end + if (q4 == 0) begin + // Conflicts with condition + q4 = 2; + end + end + +endmodule diff --git a/test/cli/verilog/t_optm_redor.v b/test/cli/verilog/t_optm_redor.v new file mode 100644 index 00000000..11df0a68 --- /dev/null +++ b/test/cli/verilog/t_optm_redor.v @@ -0,0 +1,84 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [15:0] in = crc[15:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out), + // Inputs + .in (in[15:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h162c58b1635b8d6e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [15:0] in; + output reg out; + + // TODO this should flatten into a reduction OR + always_comb begin + out = 0; + for (int i=0; i<16; i=i+1) begin + if (in[i]) begin + out = 1; + end + end + end +endmodule diff --git a/test/cli/verilog/t_order.v b/test/cli/verilog/t_order.v deleted file mode 100644 index 3613c85c..00000000 --- a/test/cli/verilog/t_order.v +++ /dev/null @@ -1,108 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - // surefire lint_off ASWEBB - // surefire lint_off ASWEMB - // surefire lint_off STMINI - // surefire lint_off CSEBEQ - - input clk; - - reg [7:0] a_to_clk_levm3; - reg [7:0] b_to_clk_levm1; - reg [7:0] c_com_levs10; - reg [7:0] d_to_clk_levm2; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v - wire [7:0] n_from_clk_lev2; // From a of t_order_a.v - wire [7:0] o_from_com_levs11; // From a of t_order_a.v - wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v - wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v - // End of automatics - - reg [7:0] cyc; initial cyc=0; - - t_order_a a ( - .one (8'h1), - /*AUTOINST*/ - // Outputs - .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), - .n_from_clk_lev2 (n_from_clk_lev2[7:0]), - .o_from_com_levs11 (o_from_com_levs11[7:0]), - .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), - // Inputs - .clk (clk), - .a_to_clk_levm3 (a_to_clk_levm3[7:0]), - .b_to_clk_levm1 (b_to_clk_levm1[7:0]), - .c_com_levs10 (c_com_levs10[7:0]), - .d_to_clk_levm2 (d_to_clk_levm2[7:0])); - - t_order_b b ( - /*AUTOINST*/ - // Outputs - .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), - // Inputs - .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); - - reg [7:0] o_from_com_levs12; - reg [7:0] o_from_com_levs13; - always @ (/*AS*/o_from_com_levs11) begin - o_from_com_levs12 = o_from_com_levs11 + 8'h1; - o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize - o_from_com_levs13 = o_from_com_levs12; - end - - reg sepassign_in; - // verilator lint_off UNOPTFLAT - wire [3:0] sepassign; - // verilator lint_on UNOPTFLAT - - // verilator lint_off UNOPT - assign #0.1 sepassign[0] = 0, - sepassign[1] = sepassign[2], - sepassign[2] = sepassign[3], - sepassign[3] = sepassign_in; - wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; - // verilator lint_on UNOPT - - always @ (posedge clk) begin - cyc <= cyc+8'd1; - sepassign_in <= 0; - if (cyc == 8'd1) begin - a_to_clk_levm3 <= 0; - d_to_clk_levm2 <= 1; - b_to_clk_levm1 <= 1; - c_com_levs10 <= 2; - sepassign_in <= 1; - end - if (cyc == 8'd2) begin - if (sepassign !== 4'b1110) $stop; - end - if (cyc == 8'd3) begin - - $display("%d %d %d %d",m_from_clk_lev1_r, - n_from_clk_lev2, - o_from_com_levs11, - o_from_comandclk_levs12); - - if (m_from_clk_lev1_r !== 8'h2) $stop; - if (o_subfrom_clk_lev3 !== 8'h2) $stop; - if (n_from_clk_lev2 !== 8'h2) $stop; - if (o_from_com_levs11 !== 8'h3) $stop; - if (o_from_com_levs13 !== 8'h5) $stop; - if (o_from_comandclk_levs12 !== 8'h5) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule diff --git a/test/cli/verilog/t_param.v b/test/cli/verilog/t_param.v new file mode 100644 index 00000000..9f84db5c --- /dev/null +++ b/test/cli/verilog/t_param.v @@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + + m1 #(PAR) m1(); + m3 #(PAR) m3(); + mnooverride #(10) mno(); + + input clk; + integer cyc=1; + reg [4:0] bitsel; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; + end + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module m1; + localparam PAR1MINUS1 = PAR1DUP-2-1; + localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly + parameter PAR1 = 0; + m2 #(PAR1MINUS1) m2 (); + + // Packed arrays + localparam [1:0][3:0] PACKED_PARAM = { 4'h3, 4'h6 }; + initial if (PACKED_PARAM != 8'h36) $stop; +endmodule + +// bug 810 +module m2 #(/*parameter*/ integer PAR2 = 10); + initial begin + $display("%x",PAR2); + if (PAR2 !== 2) $stop; + end +endmodule + +module m3; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 3) $stop; + end +endmodule + +module mnooverride; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 10) $stop; + end +endmodule diff --git a/test/cli/verilog/t_param_array.v b/test/cli/verilog/t_param_array.v new file mode 100644 index 00000000..2a58a131 --- /dev/null +++ b/test/cli/verilog/t_param_array.v @@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + typedef enum int { + PADTYPE_DEFAULT = 32'd0, + PADTYPE_GPIO, + PADTYPE_VDD, + PADTYPE_GND + } t_padtype; + + localparam int STR_PINID [0:15] + = '{ + "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" + }; + + typedef struct packed { + t_padtype padtype; + int aux; + } t_pin_descriptor; + + localparam t_pin_descriptor + PINOUT[ 1: 6] + = '{ + '{default:0, padtype:PADTYPE_GPIO, aux:1}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_VDD}, + '{default:0, padtype:PADTYPE_GND} + }; + + localparam int PINOUT_SIZE = 6; + localparam int PINOUT_WA[1:PINOUT_SIZE][3] + = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND , 0} + }; + + const int pinout_static_const[1:PINOUT_SIZE][3] + = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND , 0} + }; + + // Make sure consants propagate + checkstr #(.PINID(STR_PINID[1]), + .EXP("ERR")) + substr1 (); + checkstr #(.PINID(STR_PINID[8]), + .EXP("PA0")) + substr8 (); + + initial begin + $display("PINID1 %s", STR_PINID[1]); + $display("PINID8 %s", STR_PINID[8]); + if (STR_PINID[1] != "ERR") $stop; + if (STR_PINID[8] != "PA0") $stop; + if (pinout_static_const[1][0] != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module checkstr; + parameter int PINID = " "; + parameter int EXP = " "; + initial begin + $display("PID %s EXP %s", PINID, EXP); + if (EXP != "ERR" && EXP != "PA0") $stop; + if (PINID != EXP) $stop; + end +endmodule diff --git a/test/cli/verilog/t_param_array2.v b/test/cli/verilog/t_param_array2.v new file mode 100644 index 00000000..c4b61c39 --- /dev/null +++ b/test/cli/verilog/t_param_array2.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + localparam int c[4] = '{5, 6, 7, 8}; + a #(.p(c)) i_a (); +endmodule + +module a + #( parameter int p[4] = '{1, 2, 3, 4} ); + initial begin + if (p[0] != 5) $stop; + if (p[1] != 6) $stop; + if (p[2] != 7) $stop; + if (p[3] != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_array3.v b/test/cli/verilog/t_param_array3.v new file mode 100644 index 00000000..fb692636 --- /dev/null +++ b/test/cli/verilog/t_param_array3.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + parameter int SIZES [3:0] = '{1,2,3,4}; + typedef int calc_sums_t [3:0]; + + function calc_sums_t calc_sums; + int sum = 0; + for (int i=0; i<4; i++) begin + sum = sum + SIZES[i]; + calc_sums[i] = sum; + //TODO: calc_sums[i][31:0] = sum; + end + endfunction + + parameter int SUMS[3:0] = calc_sums(); + + initial begin + if (SUMS[0] != 4) $stop; + if (SUMS[1] != 4+3) $stop; + if (SUMS[2] != 4+3+2) $stop; + if (SUMS[3] != 4+3+2+1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_array4.v b/test/cli/verilog/t_param_array4.v new file mode 100644 index 00000000..13626edc --- /dev/null +++ b/test/cli/verilog/t_param_array4.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + parameter int SIZES [3:1] = '{10,20,30}; + parameter int SUMS3 = SIZES[3]; + parameter int SUMS2 = SIZES[2]; + parameter int SUMS1 = SIZES[1]; + + parameter int LE_SIZES [1:3] = '{10,20,30}; + parameter int LE_SUMS3 = LE_SIZES[3]; + parameter int LE_SUMS2 = LE_SIZES[2]; + parameter int LE_SUMS1 = LE_SIZES[1]; + + function int from_array(int index); + if (index != 0); return SIZES[index]; + endfunction + function int from_array_le(int index); + if (index != 0); return LE_SIZES[index]; + endfunction + + initial begin + if (SUMS1 != 30) $stop; + if (SUMS2 != 20) $stop; + if (SUMS3 != 10) $stop; + if (LE_SUMS1 != 10) $stop; + if (LE_SUMS2 != 20) $stop; + if (LE_SUMS3 != 30) $stop; + if (from_array(1) != 30) $stop; + if (from_array(2) != 20) $stop; + if (from_array(3) != 10) $stop; + if (from_array_le(1) != 10) $stop; + if (from_array_le(2) != 20) $stop; + if (from_array_le(3) != 30) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_array5.v b/test/cli/verilog/t_param_array5.v new file mode 100644 index 00000000..356c051a --- /dev/null +++ b/test/cli/verilog/t_param_array5.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +//bug1578 +module t; + parameter N = 4; + + typedef logic array_t[N]; + + parameter array_t MASK = mask_array(); + //TODO bug1578: parameter MASK = mask_array(); + + function array_t mask_array(); + for(int i = 0; i < N; i++) begin + mask_array[i] = i[0]; + end + endfunction + + array_t norm; + + initial begin + if (N != 4) $stop; + norm = mask_array(); + if (norm[0] != 1'b0) $stop; + if (norm[1] != 1'b1) $stop; + if (norm[2] != 1'b0) $stop; + if (norm[3] != 1'b1) $stop; + if (MASK[0] != 1'b0) $stop; + if (MASK[1] != 1'b1) $stop; + if (MASK[2] != 1'b0) $stop; + if (MASK[3] != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_avec.v b/test/cli/verilog/t_param_avec.v new file mode 100644 index 00000000..18806b3b --- /dev/null +++ b/test/cli/verilog/t_param_avec.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + sub #(.IDX(0), .CHK(10)) i0; + sub #(.IDX(2), .CHK(12)) i2; + sub #(.IDX(7), .CHK(17)) i7; + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub (); + function integer get_element; + input integer index; + input integer array_arg[7:0]; + get_element = array_arg[index]; + endfunction + + parameter integer IDX = 5; + parameter integer CHK = 5; + localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; + localparam element1 = array[IDX]; + localparam elementf = get_element(IDX, array); + initial begin + `checkh (element1, CHK); + `checkh (elementf, CHK); + end +endmodule diff --git a/test/cli/verilog/t_param_bit_sel.v b/test/cli/verilog/t_param_bit_sel.v new file mode 100644 index 00000000..9159485f --- /dev/null +++ b/test/cli/verilog/t_param_bit_sel.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit +// long vector. This causes the following code to fail. +// +// Other event drive simulators accept this. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // At this point it is ambiguous whether a is scalar or vector + parameter a = 1'b0; + wire b = a[0]; + // Note however b[0] is illegal. + + always @(posedge clk) begin + if (b == 1'b0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + +endmodule diff --git a/test/cli/verilog/t_param_bracket.v b/test/cli/verilog/t_param_bracket.v new file mode 100644 index 00000000..b2890ad9 --- /dev/null +++ b/test/cli/verilog/t_param_bracket.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Wilson Snyder; +// SPDX-License-Identifier: CC0-1.0 + +module t + #(parameter WIDTH = 8) + (/*AUTOARG*/ + // Outputs + o + ); + output [WIDTH-1:0] o; + localparam DEPTH = $clog2(5); + // Note single bracket below + reg [WIDTH-1:0] arid [1< y ) ? x : y; + endfunction + + function integer max4; + input integer x; + input integer y; + input integer z; + input integer w; + // MAX2 is used multiple times + max4 = max2( max2( x, y ), max2( z, w ) ); + endfunction + + localparam MAX4 = max4( 1, 1, 0, 0 ); + + initial begin + if (MAX4 != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_const_part.v b/test/cli/verilog/t_param_const_part.v new file mode 100644 index 00000000..601731f2 --- /dev/null +++ b/test/cli/verilog/t_param_const_part.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + function integer bottom_4bits; + input [7:0] i; + bottom_4bits = 0; + bottom_4bits[3:0] = i[3:0]; + endfunction + + function integer bottom_2_unknown; + input [7:0] i; + // bottom_4bits = 0; 'x + bottom_2_unknown[1:0] = i[1:0]; + endfunction + + localparam p = bottom_4bits(8'h13); + localparam bu = bottom_2_unknown(8'h13); + + initial begin + if (p != 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_ddeep_width.v b/test/cli/verilog/t_param_ddeep_width.v new file mode 100644 index 00000000..379a77e8 --- /dev/null +++ b/test/cli/verilog/t_param_ddeep_width.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use. +// SPDX-License-Identifier: CC0-1.0 + +// bug541 +module t(clk,odata); + input clk; + output [7:0] odata; + paramtest_DFFRE #(1) dffre0(clk,odata[7]); + paramtest_WRAP #(7) dffe0(clk,odata[6:0]); +endmodule + +module paramtest_WRAP(clk,q); + parameter W=1; + input clk; + output [W-1:0] q; + paramtest_DFFRE #(W) dffre0(clk,q); +endmodule + +module paramtest_DFFRE(clk,q); + parameter W=1; + parameter [W-1:0] INIT={W{1'b0}}; + input clk; + output [W-1:0] q; + reg [W-1:0] q; + always @(posedge clk) begin + q <= INIT; + end +endmodule diff --git a/test/cli/verilog/t_param_default.v b/test/cli/verilog/t_param_default.v new file mode 100644 index 00000000..d4655bcc --- /dev/null +++ b/test/cli/verilog/t_param_default.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module m #(parameter int Foo); +endmodule + +module t (/*AUTOARG*/); + + m #(10) foo(); + + initial begin + if (foo.Foo != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_first_b.v b/test/cli/verilog/t_param_first_b.v new file mode 100644 index 00000000..99e8971c --- /dev/null +++ b/test/cli/verilog/t_param_first_b.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t_param_first_b (/*AUTOARG*/ + // Outputs + par, varwidth + ); + + parameter X = 1; + parameter FIVE = 0; // Overridden + parameter TWO = 2; + + output [4:0] par; + output [X:0] varwidth; + + wire [4:0] par = X; + wire [X:0] varwidth = (FIVE==5)?TWO:0; + +endmodule diff --git a/test/cli/verilog/t_param_func.v b/test/cli/verilog/t_param_func.v new file mode 100644 index 00000000..c3a309e0 --- /dev/null +++ b/test/cli/verilog/t_param_func.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test examines Verilator against paramter definition with functions. +// Particularly the function takes in argument which is multi-dimentional. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Roland Kruse and Jie Xu. +// SPDX-License-Identifier: CC0-1.0 + +module test#( + parameter size = 4, + parameter p = sum({32'h1,32'h2,32'h3,32'h4}, size)) + + (input clk, + input logic sel, + output [p:0] res); + + logic [p:0] cc = 'h45; + + assign res = sel ? cc : {(p+1){1'b1}}; + + function integer sum; + input [3:0][31:0] values; + input int size; + + sum = 0; + + begin + for (int i = 0; i < size; i ++) + sum += values[i]; + end + endfunction + +endmodule diff --git a/test/cli/verilog/t_param_func2.v b/test/cli/verilog/t_param_func2.v new file mode 100644 index 00000000..432d2914 --- /dev/null +++ b/test/cli/verilog/t_param_func2.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + sub #(.WIDTH(4)) sub4(); + sub #(.WIDTH(8)) sub8(); + + logic [3:0] out4; + logic [7:0] out8; + + initial begin + out4 = sub4.orer(4'b1000); + out8 = sub8.orer(8'b10000000); + if (out4 != 4'b1011) $stop; + if (out8 != 8'b10111111) $stop; + out4 = sub4.orer2(4'b1000); + out8 = sub8.orer2(8'b10000000); + if (out4 != 4'b1001) $stop; + if (out8 != 8'b10011111) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + + +module sub; + parameter WIDTH = 1; + + function [WIDTH-1:0] orer; + input [WIDTH-1:0] in; + // IEEE provices no way to override this parameter, basically it's a localparam + parameter MASK_W = WIDTH - 2; + localparam [MASK_W-1:0] MASK = '1; + // verilator lint_off WIDTH + return in | MASK; + // verilator lint_on WIDTH + endfunction + + function [WIDTH-1:0] orer2; + input [WIDTH-1:0] in; + // Same param names as other function to check we disambiguate + // IEEE provices no way to override this parameter, basically it's a localparam + parameter MASK_W = WIDTH - 3; + localparam [MASK_W-1:0] MASK = '1; + // verilator lint_off WIDTH + return in | MASK; + // verilator lint_on WIDTH + endfunction +endmodule diff --git a/test/cli/verilog/t_param_if_blk.v b/test/cli/verilog/t_param_if_blk.v new file mode 100644 index 00000000..b2a71800 --- /dev/null +++ b/test/cli/verilog/t_param_if_blk.v @@ -0,0 +1,141 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. +// SPDX-License-Identifier: CC0-1.0 + +// bug648 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] datai = crc[7:0]; + wire enable = crc[8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [7:0] datao; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .datao (datao[7:0]), + // Inputs + .clk (clk), + .datai (datai[7:0]), + .enable (enable)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {56'h0, datao}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h9d550d82d38926fa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +`define FAIL 1 + +module Nested + ( + input logic clk, + input logic x, + output logic y + ); + logic t; + always_comb t = x ^ 1'b1; + + always_ff @(posedge clk) begin + if (clk) + y <= t; + end +endmodule + +module Test + ( + input logic clk, + input logic [7:0] datai, + input logic enable, + output logic [7:0] datao + ); + + // verilator lint_off BLKANDNBLK + logic [7:0] datat; + // verilator lint_on BLKANDNBLK + + for (genvar i = 0; i < 8; i++) begin + if (i%4 != 3) begin +`ifndef FAIL + logic t; + always_comb begin + t = datai[i] ^ 1'b1; + end + always_ff @(posedge clk) begin + if (clk) + datat[i] <= t; + end +`else + Nested nested_i + ( + .clk(clk), + .x(datai[i]), + .y(datat[i]) //<== via Vcellout wire + ); +`endif + + always_comb begin + casez (enable) + 1'b1: datao[i] = datat[i]; + 1'b0: datao[i] = '0; + default: datao[i] = 'x; + endcase + end + end + else begin + always_ff @(posedge clk) begin + if (clk) + datat[i] <= 0; //<== assign delayed + end + always_comb begin + casez (enable) + 1'b1: datao[i] = datat[i] ^ 1'b1; + 1'b0: datao[i] = '1; + default: datao[i] = 'x; + endcase + end + end + end +endmodule diff --git a/test/cli/verilog/t_param_local.v b/test/cli/verilog/t_param_local.v new file mode 100644 index 00000000..ceb51cab --- /dev/null +++ b/test/cli/verilog/t_param_local.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + a, y + ); + + input [1:0] a; + output [3:0] y; + + Test #(.C(2)) + test (.*); +endmodule + +module Test + #(C = 3, + localparam O = 1 << C) + (input [C-1:0] a, + output reg [O-1:0] y); + initial begin + if (O != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_mem_attr.v b/test/cli/verilog/t_param_mem_attr.v new file mode 100644 index 00000000..f9b312dc --- /dev/null +++ b/test/cli/verilog/t_param_mem_attr.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// A test case for parameterized module. +// +// When a module is instantiatied with parameter, there will be two modules in +// the tree and eventually one will be removed after param and deadifyModules. +// +// This test is to check that the removal of dead module will not cause +// compilation error. Possible error was/is seen as: +// +// pure virtual method called +// terminate called without an active exception +// %Error: Verilator aborted. Consider trying --debug --gdbbt +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire [71:0] ctrl; + wire [7:0] cl; // this line is added + + memory #(.words(72)) i_memory (.clk (clk)); + + assign ctrl = i_memory.mem[0]; + assign cl = i_memory.mem[0][7:0]; // and this line +endmodule + + +// memory module, which is used with parameter +module memory (clk); + input clk; + + parameter words = 16384, bits = 72; + + reg [bits-1 :0] mem[words-1 : 0]; + +endmodule diff --git a/test/cli/verilog/t_param_module.v b/test/cli/verilog/t_param_module.v new file mode 100644 index 00000000..69c7f1b7 --- /dev/null +++ b/test/cli/verilog/t_param_module.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test case is used for testing a modeule parameterized with a typed +// localparam. +// +// We find Verilator appears to mis-evaluate the parameter WIDTH as -16 when +// used in the test module to set the value of MSB. A number of warnings and +// errors follow, starting with: +// +// %Warning-LITENDIAN: t/t_param_module.v:42: Little bit endian vector: MSB +// < LSB of bit range: -17:0 +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2013 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 + +// bug606 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + localparam logic[4:0] WID = 16; + //localparam WID = 16; // No problem if defined like this + wire [15:0] b33; + + test #(WID) i_test_33(.clk (clk), + .b (b33)); + +endmodule + + +module test (/*AUTOARG*/ + //Inputs + clk, + // Outputs + b + ); + parameter WIDTH = 10; + localparam MSB = WIDTH - 1; + + input clk; + output wire [MSB:0] b; + + wire [MSB:0] a; + assign b = {~a[MSB-1:0], clk}; + + initial begin + if ($bits(WIDTH)!=5) $stop; // Comes from the parent! + if ($bits(MSB)!=32) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_no_parentheses.v b/test/cli/verilog/t_param_no_parentheses.v new file mode 100644 index 00000000..a5f42710 --- /dev/null +++ b/test/cli/verilog/t_param_no_parentheses.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 +// +// This is a copy of t_param.v with the parentheses around the module parameters +// removed. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + parameter PAR = 3; + + m1 #PAR m1(); + m3 #PAR m3(); + mnooverride #10 mno(); + + input clk; + integer cyc=1; + reg [4:0] bitsel; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; + end + if (cyc==1) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module m1; + localparam PAR1MINUS1 = PAR1DUP-2-1; + localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly + parameter PAR1 = 0; + m2 #PAR1MINUS1 m2 (); +endmodule + +module m2; + parameter PAR2 = 10; + initial begin + $display("%x",PAR2); + if (PAR2 !== 2) $stop; + end +endmodule + +module m3; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 3) $stop; + end +endmodule + +module mnooverride; + localparam LOC = 13; + parameter PAR = 10; + initial begin + $display("%x %x",LOC,PAR); + if (LOC !== 13) $stop; + if (PAR !== 10) $stop; + end +endmodule diff --git a/test/cli/verilog/t_param_package.v b/test/cli/verilog/t_param_package.v new file mode 100644 index 00000000..a5189145 --- /dev/null +++ b/test/cli/verilog/t_param_package.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + Test0 t0 (.val0('0)); + Test1 t1 (.val1('0)); + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +package params; + parameter P = 7; +endpackage + +module Test0 (val0); + parameter Z = 1; + input [Z : 0] val0; +endmodule + +module Test1 (val1); + input logic [params::P : 0] val1; // Fully qualified parameter +endmodule diff --git a/test/cli/verilog/t_param_real.v b/test/cli/verilog/t_param_real.v new file mode 100644 index 00000000..6fc950a8 --- /dev/null +++ b/test/cli/verilog/t_param_real.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork +// SPDX-License-Identifier: CC0-1.0 + +module mod #( + parameter real HZ = 0 +); + //verilator no_inline_module + initial begin + if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop; + if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop; + end +endmodule + +module t(); + mod #(.HZ(123.45)) mod1(); + mod #(.HZ(24.45)) mod2(); + + initial begin + if (mod1.HZ != 123.45) $stop; + if (mod2.HZ != 24.45) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_real2.v b/test/cli/verilog/t_param_real2.v new file mode 100644 index 00000000..c0286032 --- /dev/null +++ b/test/cli/verilog/t_param_real2.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module foo +#( parameter real bar = 2.0) +(); + +endmodule + +module t(); + + genvar m, r; + generate + for (m = 10; m <= 20; m+=10) begin : gen_m + for (r = 0; r <= 1; r++) begin : gen_r + localparam real lparam = m + (r + 0.5); + initial begin + if (lparam != foo_inst.bar) begin + $display("%m: lparam != foo_inst.bar (%f, %f)", + lparam, foo_inst.bar); + $stop(); + end + end + + foo #(.bar (lparam)) foo_inst (); + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_repl.v b/test/cli/verilog/t_param_repl.v new file mode 100644 index 00000000..39f22a11 --- /dev/null +++ b/test/cli/verilog/t_param_repl.v @@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter [31:0] TWENTY4 = 24; + parameter [31:0] PA = TWENTY4/8; + parameter [1:0] VALUE = 2'b10; + parameter [5:0] REPL = {PA{VALUE}}; + parameter [7:0] CONC = {REPL,VALUE}; + + parameter DBITS = 32; + parameter INIT_BYTE = 8'h1F; + parameter DWORDS_LOG2 = 7; + parameter DWORDS = (1<> M; + endfunction + + reg [95: 0] lfsr = 0; + always @(posedge clk) begin + lfsr <= (1 >> P); + end + + wire [95: 0] lfsr_w = 1 >> P; + + localparam [95: 0] lfsr_p = 1 >> P; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_type.v b/test/cli/verilog/t_param_type.v new file mode 100644 index 00000000..9fbeaa96 --- /dev/null +++ b/test/cli/verilog/t_param_type.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // counters + int cnt; + int cnt_bit ; + int cnt_byte; + int cnt_int ; + int cnt_ar1d; + int cnt_ar2d; + + // sizes + int siz_bit ; + int siz_byte; + int siz_int ; + int siz_ar1d; + int siz_ar2d; + + // add all counters + assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; + + // finish report + always @ (posedge clk) + if (cnt == 5) begin + if (siz_bit != 1) $stop(); + if (siz_byte != 8) $stop(); + if (siz_int != 32) $stop(); + if (siz_ar1d != 24) $stop(); + if (siz_ar2d != 16) $stop(); + end else if (cnt > 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // instances with various types + mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); + mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); + mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); + mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); + mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); + + // double types + mod_typ2 #(.WIDTH1(3), .WIDTH2(3), .TYP1(bit [2:0])) mod2_3_3(); + mod_typ2 #(.WIDTH1(3), .WIDTH2(5), .TYP1(bit [2:0]), .TYP2(bit[4:0])) mod2_3_5(); + +endmodule : t + + +module mod_typ #( + parameter type TYP = byte +)( + input logic clk, + output TYP cnt, + output int siz +); + + initial cnt = 0; + + always @ (posedge clk) + cnt <= cnt + 1; + + assign siz = $bits (cnt); + +endmodule + +module mod_typ2 + #( + parameter int WIDTH1 = 0, + parameter int WIDTH2 = WIDTH1, + parameter type TYP1 = byte, + // Below we need to imply that TYP2 is a type + TYP2 = TYP1 + )(); + + TYP1 t1; + TYP2 t2; + + initial begin + if ($bits(t1) != WIDTH1) $stop; + if ($bits(t2) != WIDTH2) $stop; + end + +endmodule diff --git a/test/cli/verilog/t_param_type2.v b/test/cli/verilog/t_param_type2.v new file mode 100644 index 00000000..8cdd09d7 --- /dev/null +++ b/test/cli/verilog/t_param_type2.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +package tt_pkg; + typedef enum logic [1:0] {L0, L1, L2, L3} test_t; +endpackage + +module t (/*AUTOARG*/ + // Outputs + ob + ); + + output [1:0] ob; + + import tt_pkg::*; + + test_t a; + test_t b; + + assign a = L0; + assign ob = b; + + tt_buf #(.T_t(test_t)) + u_test + (.i(a), .o(b)); + +endmodule + +module tt_buf + #( + parameter type T_t = logic [0:0] + ) + ( + input T_t i, + output T_t o + ); + assign o = i; +endmodule diff --git a/test/cli/verilog/t_param_type3.v b/test/cli/verilog/t_param_type3.v new file mode 100644 index 00000000..dca6bdc1 --- /dev/null +++ b/test/cli/verilog/t_param_type3.v @@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +typedef logic T_t; + +module t (/*AUTOARG*/ + // Outputs + o, o2, + // Inputs + i + ); + + input T_t i; + output T_t o; + output T_t o2; + + sub1 #(.T_t(T_t), .CHECK(1)) + sub1 (.i, .o); + + sub2 #(.T_t(T_t), .CHECK(2)) + sub2 (.i, .o(o2)); + + sub1 #(T_t, 1) + sub1b (i, o); + + sub2 #(T_t, 2) + sub2b (i, o2); + +endmodule + +module sub1 (i,o); + parameter type T_t = real; + localparam type T2_t = T_t; + parameter int CHECK = 0; + input T_t i; + output T2_t o; + assign o = i; + if (CHECK != 1) $error; +endmodule + +module sub2 + #( + parameter type T_t = real, + localparam type T2_t = T_t, + parameter int CHECK = 0 + ) + ( + input T_t i, + output T_t o + ); + assign o = i; + if (CHECK != 2) $error; +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End: diff --git a/test/cli/verilog/t_param_unreachable.v b/test/cli/verilog/t_param_unreachable.v new file mode 100644 index 00000000..856944f5 --- /dev/null +++ b/test/cli/verilog/t_param_unreachable.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Pierre-Henri Horrein +// SPDX-License-Identifier: CC0-1.0 + +module t (input clk); + + parameter DEPTH = 1; + reg [DEPTH-1:0] shiftreg_gen; + reg [DEPTH-1:0] shiftreg; + reg my_sr_input = '1; + + // shiftreg_gen is generated: it should not raise any warning or error + always_ff @(posedge clk) begin + shiftreg_gen[0] <= my_sr_input; + end + if (DEPTH > 1) begin + always_ff @(posedge clk) begin + shiftreg_gen[DEPTH-1:1] <= shiftreg_gen[DEPTH-2:0]; + end + end + // shiftreg is not generated: it can raise a warning + always_ff @(posedge clk) begin + shiftreg[0] <= my_sr_input; + /* verilator lint_off SELRANGE */ + if (DEPTH > 1) shiftreg[DEPTH-1:1] <= shiftreg[DEPTH-2:0]; + /* verilator lint_on SELRANGE */ + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_value.v b/test/cli/verilog/t_param_value.v new file mode 100644 index 00000000..c74e18db --- /dev/null +++ b/test/cli/verilog/t_param_value.v @@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2012 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t (/*AUTOARG*/); + +`define ASSERT(x) initial if (!(x)) $stop + // See IEEE 6.20.2 on value parameters + + localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef; + localparam signed [63:0] SIGNED =64'sh99934567_89abcdef; + localparam real REAL=1.234; + `ASSERT(UNSIGNED > 0); + `ASSERT(SIGNED < 0); + + // bullet 1 + localparam A1_WIDE = UNSIGNED; + `ASSERT($bits(A1_WIDE)==64); + + localparam A2_REAL = REAL; + `ASSERT(A2_REAL == 1.234); + + localparam A3_SIGNED = SIGNED; + `ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0); + + localparam A4_EXPR = (2'b01 + 2'b10); + `ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11); + + // bullet 2 + localparam [63:0] B_UNSIGNED = SIGNED; + `ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0); + + // bullet 3 + localparam signed C_SIGNED = UNSIGNED; + `ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0); + + localparam unsigned C_UNSIGNED = SIGNED; + `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0); + + // bullet 4 + // verilator lint_off WIDTH + localparam signed [59:0] D_SIGNED = UNSIGNED; + `ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0); + // verilator lint_on WIDTH + + // verilator lint_off WIDTH + localparam unsigned [59:0] D_UNSIGNED = SIGNED; + `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0); + // verilator lint_on WIDTH + + // bullet 6 + localparam UNSIZED = 23; + `ASSERT($bits(UNSIZED)>=32); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_param_while.v b/test/cli/verilog/t_param_while.v new file mode 100644 index 00000000..8a08f8a4 --- /dev/null +++ b/test/cli/verilog/t_param_while.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +//bug505 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter WIDTH = 33; + localparam MAX_WIDTH = 11; + localparam NUM_OUT = num_out(WIDTH); + + wire [NUM_OUT-1:0] z; + + function integer num_out; + input integer width; + num_out = 1; + while ((width + num_out - 1) / num_out > MAX_WIDTH) + num_out = num_out * 2; + endfunction + + initial begin + if (NUM_OUT != 4) $stop; + if ($bits(z) != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_param_wide_io.v b/test/cli/verilog/t_param_wide_io.v new file mode 100644 index 00000000..31168cca --- /dev/null +++ b/test/cli/verilog/t_param_wide_io.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// issue 1991 + +module t + #( + parameter[96:0] P = 97'h12344321_12344321_12344327 + ) + ( + input [P&7 - 1:0] in, + output [P&7 - 1:0] out + ); + + assign out = in; + +endmodule diff --git a/test/cli/verilog/t_param_width.v b/test/cli/verilog/t_param_width.v new file mode 100644 index 00000000..bc41be39 --- /dev/null +++ b/test/cli/verilog/t_param_width.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// issue 1991 + +module t + (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + socket #(3'b000) s0(); + socket #(3'b010) s1(); + socket #(2'b10) s2(); + socket #(2'b11) s3(); + + always_ff @ (posedge clk) begin + if (s0.ADDR != 0) $stop; + if (s1.ADDR != 2) $stop; + if (s2.ADDR != 2) $stop; + if (s3.ADDR != 3) $stop; + if ($bits(s0.ADDR) != 3) $stop; + if ($bits(s1.ADDR) != 3) $stop; + if ($bits(s2.ADDR) != 2) $stop; + if ($bits(s3.ADDR) != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module socket #(ADDR)(); + initial + $display("bits %0d, addr %b", $bits(ADDR), ADDR); +endmodule diff --git a/test/cli/verilog/t_parse_delay.v b/test/cli/verilog/t_parse_delay.v new file mode 100644 index 00000000..2b871173 --- /dev/null +++ b/test/cli/verilog/t_parse_delay.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + // verilator lint_off WIDTH + reg [6:0] myreg1; + + initial begin + myreg1 = # 100 7'd0; + myreg1 = # 100 'b0; // [#] [100] ['b0] + myreg1 = #100'b0; // [#] [100] ['b0] + myreg1 = 100'b0; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_past.v b/test/cli/verilog/t_past.v new file mode 100644 index 00000000..6f5a353b --- /dev/null +++ b/test/cli/verilog/t_past.v @@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[31:0])); + + Test2 test2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[31:0])); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + + reg [31:0] dly0; + reg [31:0] dly1; + reg [31:0] dly2; + reg [31:0] dly3; + + // If called in an assertion, sequence, or property, the appropriate clocking event. + // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. + // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. + // Otherwise, if called in a procedure, the inferred clock + // Otherwise, default clocking + + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + dly2 <= dly1; + dly3 <= dly2; + // $past(expression, ticks, expression, clocking) + // In clock expression + if (dly0 != $past(in)) $stop; + if (dly0 != $past(in,1)) $stop; + if (dly1 != $past(in,2)) $stop; + // $sampled(expression) -> expression + if (in != $sampled(in)) $stop; + end + + assert property (@(posedge clk) dly0 == $past(in)); + +endmodule + +module Test2 (/*AUTOARG*/ + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + + reg [31:0] dly0; + reg [31:0] dly1; + + always @(posedge clk) begin + dly0 <= in; + dly1 <= dly0; + end + + default clocking @(posedge clk); endclocking + assert property (@(posedge clk) $time < 40 || dly1 == $past(in, 2)); + +endmodule diff --git a/test/cli/verilog/t_past_funcs.v b/test/cli/verilog/t_past_funcs.v new file mode 100644 index 00000000..2ee24f4a --- /dev/null +++ b/test/cli/verilog/t_past_funcs.v @@ -0,0 +1,105 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Peter Monsson. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + wire [31:0] in = cyc; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[31:0])); + + Test2 test2 (/*AUTOINST*/ + // Inputs + .clk (clk), + .in (in[31:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + + reg [31:0] dly0 = 0; + reg [31:0] dly1 = 1; + reg [31:0] dly2 = -1; + + // If called in an assertion, sequence, or property, the appropriate clocking event. + // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. + // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. + // Otherwise, if called in a procedure, the inferred clock + // Otherwise, default clocking + + always @(posedge clk) begin + dly0 <= in; + dly1 <= in; + dly2 <= in; + // In clock expression + $write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0)); + if ($rose(dly0[4])) $stop; + if ($fell(dly1[4])) $stop; + if ($stable(dly2)) $stop; + if (!$changed(dly2)) $stop; + end + + assert property (@(posedge clk) $rose(dly0) || dly0%2==0); + assert property (@(posedge clk) $fell(dly1) || dly1%2==1); + assert property (@(posedge clk) !$stable(dly2)); + assert property (@(posedge clk) $changed(dly2)); +endmodule + + +module Test2 (/*AUTOARG*/ + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + + reg [31:0] dly0; + reg [31:0] dly1 = 1; + reg [31:0] dly2; + + always @(posedge clk) begin + dly0 <= in; + dly1 <= in; + dly2 <= in; + if ($rose(dly0[31:4])) $stop; + if ($fell(dly1[31:4])) $stop; + if (!$stable(dly2[31:4])) $stop; + if ($changed(dly2[31:4])) $stop; + end + + default clocking @(posedge clk); endclocking + assert property ($rose(dly0[0]) || dly0%2==0); + + default clocking @(posedge clk); endclocking + assert property ($fell(dly1[0]) || dly1%2==1); + + default clocking @(posedge clk); endclocking + assert property ($stable(dly2[31:4])); + assert property (!$changed(dly2[31:4])); +endmodule diff --git a/test/cli/verilog/t_pp_display.v b/test/cli/verilog/t_pp_display.v new file mode 100644 index 00000000..4a0fcca0 --- /dev/null +++ b/test/cli/verilog/t_pp_display.v @@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + wire d1 = 1'b1; + wire d2 = 1'b1; + wire d3 = 1'b1; + wire o1,o2,o3; + add1 add1 (d1,o1); + add2 add2 (d2,o2); + +`define ls left_side +`define rs right_side +`define noarg na//note extra space +`define thru(x) x +`define thruthru `ls `rs // Doesn't expand +`define msg(x,y) `"x: `\`"y`\`"`" +`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string + initial begin + //$display(`msg( \`, \`)); // Illegal + $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); + $display(`msg(left side,right side)); + $display(`msg( left side , right side )); + $display(`msg( `ls , `rs )); + $display(`msg( `noarg , `rs )); + $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); + $display(`msg(`noarg,`noarg`noarg)); + $display(`msg( `thruthru , `thruthru )); // Results vary between simulators + $display(`left(`msg( left side , right side ), left_replaced)); + //$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error +`ifndef VCS // Sim bug - wrong number of arguments, but we're right + $display(`msg(`thru(),)); // Empty +`endif + $display(`msg(`thru(left side),`thru(right side))); + $display(`msg( `thru( left side ) , `thru( right side ) )); +`ifndef NC + $display(`"standalone`"); +`endif + +`ifdef VERILATOR + // Illegal on some simulators, as the "..." crosses two lines +`define twoline first \ + second + $display(`msg(twoline, `twoline)); +`endif + + $display("Line %0d File \"%s\"",`__LINE__,`__FILE__); + + //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +`define ADD_UP(a,c) \ +wire tmp_``a = a; \ +wire tmp_``c = tmp_``a + 1; \ +assign c = tmp_``c ; + +module add1 ( input wire d1, output wire o1); + `ADD_UP(d1,o1) // expansion is OK +endmodule +module add2 ( input wire d2, output wire o2); + `ADD_UP( d2 , o2 ) // expansion is bad +endmodule +// `ADD_UP( \d3 , \o3 ) // This really is illegal diff --git a/test/cli/verilog/t_pp_pragmas.v b/test/cli/verilog/t_pp_pragmas.v new file mode 100644 index 00000000..2da128a3 --- /dev/null +++ b/test/cli/verilog/t_pp_pragmas.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`timescale 1ns/10ps +`verilog + +`suppress_faults +`nosuppress_faults +`enable_portfaults +`disable_portfaults + +`delay_mode_distributed +`delay_mode_path +`delay_mode_unit +`delay_mode_zero + +`default_decay_time 1 +`default_decay_time 1.0 +`default_decay_time infinite +// unsupported (recommended not to): `default_trireg_strength 10 + +`default_nettype wire +// unsupported: `default_nettype tri +// unsupported: `default_nettype tri0 +// unsupported: `default_nettype wand +// unsupported: `default_nettype triand +// unsupported: `default_nettype wor +// unsupported: `default_nettype trior +// unsupported: `default_nettype trireg +`default_nettype none + +`autoexpand_vectornets + +`accelerate +`noaccelerate +`expand_vectornets +`noexpand_vectornets +`remove_gatenames +`noremove_gatenames +`remove_netnames +`noremove_netnames +`resetall + +// unsupported: `unconnected_drive pull1 +// unsupported: `unconnected_drive pull0 +`nounconnected_drive + +`line 100 "hallo.v" 0 + +// unsupported: `uselib file=../moto_lib.v +// unsupported: `uselib dir=../lib.dir libext=.v + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_real_param.v b/test/cli/verilog/t_real_param.v new file mode 100644 index 00000000..16737272 --- /dev/null +++ b/test/cli/verilog/t_real_param.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 + +module foo + #( parameter real bar = 2.0) + (); +endmodule + +module t(); + genvar m, r; + generate + for (m = 10; m <= 20; m+=10) begin : gen_m + for (r = 0; r <= 1; r++) begin : gen_r + localparam real lparam = m + (r + 0.5); + initial begin + if (lparam != foo_inst.bar) begin + $display("%m: lparam != foo_inst.bar (%f, %f)", + lparam, foo_inst.bar); + $stop(); + end + end + + foo #(.bar (lparam)) foo_inst (); + end + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_reloop_offset.v b/test/cli/verilog/t_reloop_offset.v new file mode 100755 index 00000000..b4bfc419 --- /dev/null +++ b/test/cli/verilog/t_reloop_offset.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`define show(x) $display("oarray[%2d] is %2d", x, oarray[x]) + +module t (/*AUTOARG*/); + + int iarray [63:0]; + int oarray [63:0]; + + initial begin + for (int i = 0; i < 64 ; i = i + 1) begin + iarray[i] = i; + oarray[i] = 0; + end + + for (int i = 0; i < 63; i = i + 1) begin + oarray[i] = iarray[i + 1]; + end + + $display("shift down 1"); + `show(63); + `show(62); + `show(61); + `show(32); + `show(2); + `show(1); + `show(0); + + for (int i = 63; i >= 2 ; i = i - 1) begin + oarray[i] = iarray[i - 2]; + end + + $display("shift up 2"); + `show(63); + `show(62); + `show(61); + `show(32); + `show(2); + `show(1); + `show(0); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_rnd.v b/test/cli/verilog/t_rnd.v new file mode 100644 index 00000000..0cc25998 --- /dev/null +++ b/test/cli/verilog/t_rnd.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg _ranit; + + reg [2:0] a; + reg [33:0] wide; + reg unused_r; + + initial _ranit = 0; + + always @ (posedge clk) begin : blockName + begin // Verify begin/begin is legal + unused_r <= 1'b1; + end + begin end // Verify empty is legal + end + + wire one = 1'b1; + wire [7:0] rand_bits = 8'b01xx_xx10; + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + // + a = 3'b1xx; + wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; + if (one !== 1'b1) $stop; + if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // verilator lint_off UNUSED + wire _unused_ok = |{1'b1, wide}; + // verilator lint_on UNUSED + +endmodule diff --git a/test/cli/verilog/t_runflag.v b/test/cli/verilog/t_runflag.v new file mode 100644 index 00000000..ff98975d --- /dev/null +++ b/test/cli/verilog/t_runflag.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_sc_names.v b/test/cli/verilog/t_sc_names.v new file mode 100644 index 00000000..13bcd437 --- /dev/null +++ b/test/cli/verilog/t_sc_names.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Edgar E. Iglesias. +// SPDX-License-Identifier: CC0-1.0 + +module t ( + clk + ); + input clk; +endmodule diff --git a/test/cli/verilog/t_select_2d.v b/test/cli/verilog/t_select_2d.v new file mode 100644 index 00000000..bbe492e5 --- /dev/null +++ b/test/cli/verilog/t_select_2d.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [4:0] cnt_i = (crc[4:0] <= 5'd17) ? crc[4:0] : 5'd0; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [63:0] out_o; // From test of Test.v + // End of automatics + + Test test(/*AUTOINST*/ + // Outputs + .out_o (out_o[63:0]), + // Inputs + .cnt_i (cnt_i[4:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = out_o; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h1f324087bbba0bfa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + (input logic [4:0] cnt_i, + output logic [63:0] out_o); + + logic [17:0][63:0] data; + initial begin + for (int a = 0; a < 18; ++a) + data[a] = {8{a[7:0]}}; + end + + // verilator lint_off WIDTH + assign out_o = data[5'd17 - cnt_i]; + +endmodule diff --git a/test/cli/verilog/t_select_bound1.v b/test/cli/verilog/t_select_bound1.v new file mode 100644 index 00000000..af2861c6 --- /dev/null +++ b/test/cli/verilog/t_select_bound1.v @@ -0,0 +1,92 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug823 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[2:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'ha9d3a7a69d2bea75 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, mask, + // Inputs + clk, in + ); + + input clk; + input [2:0] in; + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] p = 11'h1ac; + + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= p[15 + in -: 5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end + +endmodule diff --git a/test/cli/verilog/t_select_bound2.v b/test/cli/verilog/t_select_bound2.v new file mode 100644 index 00000000..681a9245 --- /dev/null +++ b/test/cli/verilog/t_select_bound2.v @@ -0,0 +1,92 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug823 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [6:0] in = crc[6:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[6:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4e9d3a74e9d3f656 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, mask, + // Inputs + clk, in + ); + + input clk; + input [6:0] in; // Note much wider than any index + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] p = 11'h1ac; + + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= p[15 + in -: 5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end + +endmodule diff --git a/test/cli/verilog/t_select_index.v b/test/cli/verilog/t_select_index.v new file mode 100644 index 00000000..65ad3966 --- /dev/null +++ b/test/cli/verilog/t_select_index.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off NBAJAM + + input clk; + reg [7:0] _ranit; + + reg [2:0] a; + reg [7:0] vvector; + reg [7:0] vvector_flip; + + // surefire lint_off STMINI + initial _ranit = 0; + + always @ (posedge clk) begin + a <= a + 3'd1; + vvector[a] <= 1'b1; // This should use "old" value for a + vvector_flip[~a] <= 1'b1; // This should use "old" value for a + // + //======== + if (_ranit==8'd0) begin + _ranit <= 8'd1; + $write("[%0t] t_select_index: Running\n", $time); + vvector <= 0; + vvector_flip <= 0; + a <= 3'b1; + end + else _ranit <= _ranit + 8'd1; + // + if (_ranit==8'd3) begin + $write("%x %x\n",vvector,vvector_flip); + if (vvector !== 8'b0000110) $stop; + if (vvector_flip !== 8'b0110_0000) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_select_index2.v b/test/cli/verilog/t_select_index2.v new file mode 100644 index 00000000..87cca656 --- /dev/null +++ b/test/cli/verilog/t_select_index2.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [7:0] x; + wire [3:0] en; + wire sel; + wire a; + + // bug675 + generate + genvar g_k; + for ( g_k = 0; g_k < 8; g_k = g_k + 1 ) + begin: g_index + always @* begin + // Note this isn't a genif, but normal if + // verilator lint_off SELRANGE + if(g_k<4) begin + x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; + end + else begin + x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; + end + // verilator lint_on SELRANGE + end + end + endgenerate + +endmodule diff --git a/test/cli/verilog/t_select_lhs_oob.v b/test/cli/verilog/t_select_lhs_oob.v new file mode 100644 index 00000000..b3447084 --- /dev/null +++ b/test/cli/verilog/t_select_lhs_oob.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + reg [6:0] mem1d; + reg [6:0] mem2d [5:0]; + reg [6:0] mem3d [4:0][5:0]; + + integer i,j,k; + + // Four different test cases for out of bounds + // = + // <= + // Continuous assigns + // Output pin interconnect (also covers cont assigns) + // Each with both bit selects and array selects + + initial begin + mem1d[0] = 1'b0; + i=7; + mem1d[i] = 1'b1; + if (mem1d[0] !== 1'b0) $stop; + // + for (i=0; i<8; i=i+1) begin + for (j=0; j<8; j=j+1) begin + for (k=0; k<8; k=k+1) begin + mem1d[k] = k[0]; + mem2d[j][k] = j[0]+k[0]; + mem3d[i][j][k] = i[0]+j[0]+k[0]; + end + end + end + for (i=0; i<5; i=i+1) begin + for (j=0; j<6; j=j+1) begin + for (k=0; k<7; k=k+1) begin + if (mem1d[k] !== k[0]) $stop; + if (mem2d[j][k] !== j[0]+k[0]) $stop; + if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; + end + end + end + end + + integer wi; + wire [31:0] wd = cyc; + reg [31:0] reg2d[6:0]; + always @ (posedge clk) reg2d[wi[2:0]] <= wd; + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd); +`endif + cyc <= cyc + 1; + if (cyc<10) begin + wi <= 0; + end + else if (cyc==10) begin + wi <= 1; + end + else if (cyc==11) begin + if (reg2d[0] !== 10) $stop; + wi <= 6; + end + else if (cyc==12) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + wi <= 7; // Will be ignored + end + else if (cyc==13) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; + end + else if (cyc==14) begin + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_select_lhs_oob2.v b/test/cli/verilog/t_select_lhs_oob2.v new file mode 100644 index 00000000..10cff1cf --- /dev/null +++ b/test/cli/verilog/t_select_lhs_oob2.v @@ -0,0 +1,142 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [63:0] out; // From test of Test.v + // End of automatics + + wire reset_l = ~(cyc<15); + wire [63:0] d = crc[63:0]; + wire [8:0] t_wa = crc[8:0]; + wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; + + Test test (/*AUTOINST*/ + // Outputs + .out (out[63:0]), + // Inputs + .clk (clk), + .reset_l (reset_l), + .t_wa (t_wa[8:0]), + .d (d[63:0]), + .t_addr (t_addr[8:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h421a41d1541ea652 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, reset_l, t_wa, d, t_addr + ); + input clk; + input reset_l; + + reg [63:0] m_w0 [47:0]; + reg [63:0] m_w1 [23:0]; + reg [63:0] m_w2 [23:0]; + reg [63:0] m_w3 [23:0]; + reg [63:0] m_w4 [23:0]; + reg [63:0] m_w5 [23:0]; + + input [8:0] t_wa; + input [63:0] d; + + always @ (posedge clk) begin + if (~reset_l) begin : blk + integer i; + + for (i=0; i<48; i=i+1) begin + m_w0[i] <= 64'h0; + end + + for (i=0; i<24; i=i+1) begin + m_w1[i] <= 64'h0; + m_w2[i] <= 64'h0; + m_w3[i] <= 64'h0; + m_w4[i] <= 64'h0; + m_w5[i] <= 64'h0; + end + end + else begin + casez (t_wa[8:6]) + 3'd0: m_w0[t_wa[5:0]] <= d; + 3'd1: m_w1[t_wa[4:0]] <= d; + 3'd2: m_w2[t_wa[4:0]] <= d; + 3'd3: m_w3[t_wa[4:0]] <= d; + 3'd4: m_w4[t_wa[4:0]] <= d; + default: m_w5[t_wa[4:0]] <= d; + endcase + end + end + + input [8:0] t_addr; + + wire [63:0] t_w0 = m_w0[t_addr[5:0]]; + wire [63:0] t_w1 = m_w1[t_addr[4:0]]; + wire [63:0] t_w2 = m_w2[t_addr[4:0]]; + wire [63:0] t_w3 = m_w3[t_addr[4:0]]; + wire [63:0] t_w4 = m_w4[t_addr[4:0]]; + wire [63:0] t_w5 = m_w5[t_addr[4:0]]; + + output reg [63:0] out; + always @* begin + casez (t_addr[8:6]) + 3'd0: out = t_w0; + 3'd1: out = t_w1; + 3'd2: out = t_w2; + 3'd3: out = t_w3; + 3'd4: out = t_w4; + default: out = t_w5; + endcase + end + +endmodule diff --git a/test/cli/verilog/t_select_little.v b/test/cli/verilog/t_select_little.v new file mode 100644 index 00000000..2b7b9e93 --- /dev/null +++ b/test/cli/verilog/t_select_little.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // verilator lint_off LITENDIAN + wire [10:41] sel2 = crc[31:0]; + wire [10:100] sel3 = {crc[26:0],crc}; + + wire out20 = sel2[{1'b0,crc[3:0]} + 11]; + wire [3:0] out21 = sel2[13 : 16]; + wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; + wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; + + wire out30 = sel3[{2'b0,crc[3:0]} + 11]; + wire [3:0] out31 = sel3[13 : 16]; + wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; + wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; + + // Aggregate outputs into a single result vector + wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + + reg [19:50] sel1; + initial begin + // Path clearing + // 122333445 + // 826048260 + sel1 = 32'h12345678; + if (sel1 != 32'h12345678) $stop; + if (sel1[47 : 50] != 4'h8) $stop; + if (sel1[31 : 34] != 4'h4) $stop; + if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] + if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33); + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h28bf65439eb12c00 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_select_little_pack.v b/test/cli/verilog/t_select_little_pack.v new file mode 100644 index 00000000..e265f3b1 --- /dev/null +++ b/test/cli/verilog/t_select_little_pack.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // No endian warning here + reg [7:0] pack [3:0]; + + initial begin + pack[0] = 8'h78; + pack[1] = 8'h88; + pack[2] = 8'h98; + pack[3] = 8'hA8; + if (pack[0] !== 8'h78) $stop; + if (pack[1] !== 8'h88) $stop; + if (pack[2] !== 8'h98) $stop; + if (pack[3] !== 8'hA8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_select_param.v b/test/cli/verilog/t_select_param.v new file mode 100644 index 00000000..a8830d6b --- /dev/null +++ b/test/cli/verilog/t_select_param.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + parameter [ BMSB : BLSB ] B = A[23:20]; // 3 + parameter A = 32'h12345678; + parameter BLSB = A[16+:4]; // 4 + parameter BMSB = A[7:4]; // 7 + + initial begin + if (B !== 4'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_select_plus_mul_pow2.v b/test/cli/verilog/t_select_plus_mul_pow2.v new file mode 100644 index 00000000..d533b88a --- /dev/null +++ b/test/cli/verilog/t_select_plus_mul_pow2.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Conor McCullough. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [63:0] from = 64'h0706050403020100; + reg [7:0] to; + reg [2:0] bitn; + reg [7:0] cyc; initial cyc=0; + + always @* begin + to = from[bitn * 8 +: 8]; + end + + always @ (posedge clk) begin + cyc <= cyc + 8'd1; + case (cyc) + 8'd00: begin bitn<=3'd0; end + 8'd01: begin bitn<=3'd1; end + 8'd02: begin bitn<=3'd2; end + 8'd03: begin bitn<=3'd3; end + 8'd04: begin bitn<=3'd4; end + 8'd05: begin bitn<=3'd5; end + 8'd06: begin bitn<=3'd6; end + 8'd07: begin bitn<=3'd7; end + 8'd08: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; + endcase + case (cyc) + 8'd00: ; + 8'd01: begin if (to !== 8'h00) $stop; end + 8'd02: begin if (to !== 8'h01) $stop; end + 8'd03: begin if (to !== 8'h02) $stop; end + 8'd04: begin if (to !== 8'h03) $stop; end + 8'd05: begin if (to !== 8'h04) $stop; end + 8'd06: begin if (to !== 8'h05) $stop; end + 8'd07: begin if (to !== 8'h06) $stop; end + 8'd08: begin if (to !== 8'h07) $stop; end + default: $stop; + endcase + end + +endmodule diff --git a/test/cli/verilog/t_select_runtime_range.v b/test/cli/verilog/t_select_runtime_range.v new file mode 100644 index 00000000..b43330e1 --- /dev/null +++ b/test/cli/verilog/t_select_runtime_range.v @@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + reg [43:0] mi; + reg [5:0] index; + integer indexi; + reg read; + + initial begin + // Static + mi = 44'b01010101010101010101010101010101010101010101; + if (mi[0] !== 1'b1) $stop; + if (mi[1 -: 2] !== 2'b01) $stop; +`ifdef VERILATOR + // verilator lint_off SELRANGE + if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop; + if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop; + if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop; + // verilator lint_on SELRANGE +`else + if (mi[-1] !== 1'bx) $stop; + if (mi[0 -: 2] !== 2'b1x) $stop; + if (mi[-1 -: 2] !== 2'bxx) $stop; +`endif + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + mi = 44'h123; + end + if (cyc==2) begin + index = 6'd43; + indexi = 43; + end + if (cyc==3) begin + read = mi[index]; + if (read!==1'b0) $stop; + read = mi[indexi]; + if (read!==1'b0) $stop; + end + if (cyc==4) begin + index = 6'd44; + indexi = 44; + end + if (cyc==5) begin + read = mi[index]; + $display("-Illegal read value: %x",read); + //if (read!==1'b1 && read!==1'bx) $stop; + read = mi[indexi]; + $display("-Illegal read value: %x",read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc==6) begin + indexi = -1; + end + if (cyc==7) begin + read = mi[indexi]; + $display("-Illegal read value: %x",read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_select_set.v b/test/cli/verilog/t_select_set.v new file mode 100644 index 00000000..30054a00 --- /dev/null +++ b/test/cli/verilog/t_select_set.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + reg [63:0] inwide; + reg [39:0] addr; + + integer cyc; initial cyc=1; + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write ("%x %x\n", cyc, addr); +`endif + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + addr <= 40'h12_3456_7890; + end + if (cyc==2) begin + if (addr !== 40'h1234567890) $stop; + addr[31:0] <= 32'habcd_efaa; + end + if (cyc==3) begin + if (addr !== 40'h12abcdefaa) $stop; + addr[39:32] <= 8'h44; + inwide <= 64'hffeeddcc_11334466; + end + if (cyc==4) begin + if (addr !== 40'h44abcdefaa) $stop; + addr[31:0] <= inwide[31:0]; + end + if (cyc==5) begin + if (addr !== 40'h4411334466) $stop; + $display ("Flip [%x]\n", inwide[3:0]); + addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; + end + if (cyc==6) begin + if (addr !== 40'h4411334426) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_slice_cond.v b/test/cli/verilog/t_slice_cond.v new file mode 100644 index 00000000..8560bbce --- /dev/null +++ b/test/cli/verilog/t_slice_cond.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + dataout, + // Inputs + clk, sel, d0, d1 + ); + + input clk; + input sel; + + logic [7:0] data [1:0][3:0]; + input [7:0] d0, d1; + + output wire [8*2*4-1:0] dataout; + + always_comb begin + for ( integer j = 0; j <= 1; j++ ) begin + if (sel) + data[j] = '{ d0, d1, 8'h00, 8'h00 }; + else + data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; + end + for ( integer j = 0; j <= 1; j++ ) begin + data[j] = sel + ? '{ d0, d1, 8'h00, 8'h00 } + : '{ 8'h00, 8'h00, 8'h00, 8'h00 }; + end + end + + assign dataout = {data[0][0], data[0][1], data[0][2], data[0][3], + data[1][0], data[1][1], data[1][2], data[1][3]}; + +endmodule diff --git a/test/cli/verilog/t_slice_init.v b/test/cli/verilog/t_slice_init.v new file mode 100644 index 00000000..b1901f7a --- /dev/null +++ b/test/cli/verilog/t_slice_init.v @@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk, d0, d1 + ); + + input clk; + input [7:0] d0, d1; + + logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, + '{ '1, '1, 8'h11, 8'h22 }}; + logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, + '{ '1, '1, 8'h11, 8'h22 }}; + + logic [7:0] data [1:0][3:0]; + logic [7:0] datl [0:1][0:3]; + + initial begin + data = '{ '{ d0, d1, 8'hfe, 8'hed }, + '{ d1, d1, 8'h11, 8'h22 }}; + data[0] = '{ d0, d1, 8'h19, 8'h39 }; + + datl = '{ '{ d0, d1, 8'hfe, 8'hed }, + '{ d1, d1, 8'h11, 8'h22 }}; + datl[0] = '{ d0, d1, 8'h19, 8'h39 }; + +`ifdef TEST_VERBOSE + $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); + $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); + $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); + $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); +`endif + if (inia[0][0] !== 8'h22) $stop; + if (inia[0][1] !== 8'h11) $stop; + if (inia[1][0] !== 8'hed) $stop; + if (inia[1][1] !== 8'hfe) $stop; + + if (inil[0][2] !== 8'hfe) $stop; + if (inil[0][3] !== 8'hed) $stop; + if (inil[1][2] !== 8'h11) $stop; + if (inil[1][3] !== 8'h22) $stop; + + if (data[0][0] !== 8'h39) $stop; + if (data[0][1] !== 8'h19) $stop; + if (data[1][0] !== 8'hed) $stop; + if (data[1][1] !== 8'hfe) $stop; + + if (datl[0][2] !== 8'h19) $stop; + if (datl[0][3] !== 8'h39) $stop; + if (datl[1][2] !== 8'h11) $stop; + if (datl[1][3] !== 8'h22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_static_elab.v b/test/cli/verilog/t_static_elab.v new file mode 100644 index 00000000..afb29e37 --- /dev/null +++ b/test/cli/verilog/t_static_elab.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Simple static elaboration case +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + typedef struct packed { + logic [ 31 : 0 ] _five; + } five_t; + + typedef enum { + LOW_FIVE = 32'hdeadbeef, + HIGH_FIVE + } five_style_t; + + function five_t gimme_five (); + automatic five_t result; + + result._five = 5; + + return result; + endfunction + + function five_style_t gimme_high_five (); + automatic five_style_t result; + + result = HIGH_FIVE; + + return result; + endfunction + + localparam five_t FIVE = gimme_five(); + localparam five_style_t THE_HIGH_FIVE = gimme_high_five(); + + initial begin + if (FIVE._five != 5) begin + $display("%%Error: Got 0b%b instead of 5", FIVE._five); + $stop; + end + + if (THE_HIGH_FIVE != HIGH_FIVE) begin + $display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_table_fsm.v b/test/cli/verilog/t_table_fsm.v new file mode 100644 index 00000000..f4d57428 --- /dev/null +++ b/test/cli/verilog/t_table_fsm.v @@ -0,0 +1,160 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire myevent; // From test of Test.v + wire myevent_pending; // From test of Test.v + wire [1:0] state; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .state (state[1:0]), + .myevent (myevent), + .myevent_pending (myevent_pending), + // Inputs + .clk (clk), + .reset (reset)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, myevent_pending,myevent,state}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + reset <= (cyc<2); + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4e93a74bd97b25ef + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + state, myevent, myevent_pending, + // Inputs + clk, reset + ); + input clk; + input reset; + output [1:0] state; + output myevent; + output myevent_pending; + + reg [5:0] count = 0; + always @ (posedge clk) + if (reset) count <= 0; + else count <= count + 1; + + reg myevent = 1'b0; + always @ (posedge clk) + myevent <= (count == 6'd27); + + reg myevent_done; + reg hickup_ready; + reg hickup_done; + + localparam STATE_ZERO = 0; + localparam STATE_ONE = 1; + localparam STATE_TWO = 2; + + reg [1:0] state = STATE_ZERO; + reg state_start_myevent = 1'b0; + reg state_start_hickup = 1'b0; + reg myevent_pending = 1'b0; + always @ (posedge clk) begin + state <= state; + myevent_pending <= myevent_pending || myevent; + state_start_myevent <= 1'b0; + state_start_hickup <= 1'b0; + case (state) + STATE_ZERO: + if (myevent_pending) begin + state <= STATE_ONE; + myevent_pending <= 1'b0; + state_start_myevent <= 1'b1; + end else if (hickup_ready) begin + state <= STATE_TWO; + state_start_hickup <= 1'b1; + end + + STATE_ONE: + if (myevent_done) + state <= STATE_ZERO; + + STATE_TWO: + if (hickup_done) + state <= STATE_ZERO; + + default: + ; /* do nothing */ + endcase + end + + reg [3:0] myevent_count = 0; + always @ (posedge clk) + if (state_start_myevent) + myevent_count <= 9; + else if (myevent_count > 0) + myevent_count <= myevent_count - 1; + + initial myevent_done = 1'b0; + always @ (posedge clk) + myevent_done <= (myevent_count == 0); + + reg [4:0] hickup_backlog = 2; + always @ (posedge clk) + if (state_start_myevent) + hickup_backlog <= hickup_backlog - 1; + else if (state_start_hickup) + hickup_backlog <= hickup_backlog + 1; + + initial hickup_ready = 1'b1; + always @ (posedge clk) + hickup_ready <= (hickup_backlog < 3); + + reg [3:0] hickup_count = 0; + always @ (posedge clk) + if (state_start_hickup) + hickup_count <= 10; + else if (hickup_count > 0) + hickup_count <= hickup_count - 1; + + initial hickup_done = 1'b0; + always @ (posedge clk) + hickup_done <= (hickup_count == 1); + +endmodule diff --git a/test/cli/verilog/t_time_literals.v b/test/cli/verilog/t_time_literals.v new file mode 100644 index 00000000..c4de1097 --- /dev/null +++ b/test/cli/verilog/t_time_literals.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under The Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +`timescale 1ns/1ps + +module t; + time t; + + // realtime value scaled to timeunit, rounded to timeprecision + initial begin + // verilator lint_off REALCVT + t = 1s; `checkd(t, 64'd1000000000); + t = 2ms; `checkd(t, 2000000); + t = 1ms; `checkd(t, 1000000); + t = 1us; `checkd(t, 1000); + t = 1ns; `checkd(t, 1); + t = 1ps; `checkd(t, 0); // Below precision + t = 1fs; `checkd(t, 0); + + t = 2.3ps; `checkd(t, 0); + t = 2.4us; `checkd(t, 2400); + // verilator lint_on REALCVT + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_tri_array_bufif.v b/test/cli/verilog/t_tri_array_bufif.v new file mode 100644 index 00000000..44489b7f --- /dev/null +++ b/test/cli/verilog/t_tri_array_bufif.v @@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + parameter DW = 4; + wire [3:0] drv_a = crc[3:0]; + wire [3:0] drv_b = crc[7:4]; + wire [3:0] drv_e = crc[19:16]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [DW-1:0] drv; // To/From test1 of Test1.v + wire [DW-1:0] drv2; // From test2 of Test2.v + // End of automatics + + Test1 test1 (/*AUTOINST*/ + // Inouts + .drv (drv[DW-1:0]), + // Inputs + .drv_a (drv_a[DW-1:0]), + .drv_b (drv_b[DW-1:0]), + .drv_e (drv_e[DW-1:0])); + Test2 test2 (/*AUTOINST*/ + // Outputs + .drv2 (drv2[DW-1:0]), + // Inputs + .drv_a (drv_a[DW-1:0]), + .drv_b (drv_b[DW-1:0]), + .drv_e (drv_e[DW-1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, drv}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + if (drv2 != drv) $stop; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hd95d216c5a2945d0 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test1 #( + parameter DW = 4 +)( + input wire [DW-1:0] drv_a, + input wire [DW-1:0] drv_b, + input wire [DW-1:0] drv_e, + inout wire [DW-1:0] drv +); + + wire drv_0, drv_1, drv_2, drv_3; + bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]); + bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]); + bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]); + bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]); + bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]); + bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]); + bufif1 + bufa3 (drv_3, drv_a[3], drv_e[3]), + bufb3 (drv_3, drv_b[3], ~drv_e[3]); + assign drv = {drv_3,drv_2,drv_1,drv_0}; + +endmodule + +module Test2 #( + parameter DW = 4 +)( + input wire [DW-1:0] drv_a, + input wire [DW-1:0] drv_b, + input wire [DW-1:0] drv_e, + inout wire [DW-1:0] drv2 +); + + wire [DW-1:0] drv_all; + bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e); + // Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e); + bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]}, + {drv_b[3], drv_b[2], drv_b[1], drv_b[0]}, + {~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]}); + assign drv2 = drv_all; + +endmodule diff --git a/test/cli/verilog/t_tri_array_pull.v b/test/cli/verilog/t_tri_array_pull.v new file mode 100644 index 00000000..b29d1d5b --- /dev/null +++ b/test/cli/verilog/t_tri_array_pull.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Rod Steward. +// SPDX-License-Identifier: CC0-1.0 + +module IOBUF ( input T, input I, output O, inout IO ); + assign O = IO; + assign IO = T ? 1'bz : I; +endmodule + +module t + ( + input [7:0] inlines, + output [7:0] outlines, + inout [7:0] iolines, + + input inctrl + ); + + generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D + IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) ); + pullup d_pup (iolines[i]); + end + endgenerate + + IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) ); + pullup d_0_pup (iolines[0]); + + IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) ); + pullup d_1_pup (iolines[1]); + + IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) ); + pullup d_2_pup (iolines[2]); + + IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) ); + pullup d_3_pup (iolines[3]); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_tri_eqcase.v b/test/cli/verilog/t_tri_eqcase.v new file mode 100644 index 00000000..a922a4b9 --- /dev/null +++ b/test/cli/verilog/t_tri_eqcase.v @@ -0,0 +1,129 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [3:0] drv_a = crc[3:0]; + wire [3:0] drv_b = crc[7:4]; + wire [3:0] drv_e = crc[19:16]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [8:0] match1; // From test1 of Test1.v + wire [8:0] match2; // From test2 of Test2.v + // End of automatics + + Test1 test1 (/*AUTOINST*/ + // Outputs + .match1 (match1[8:0]), + // Inputs + .drv_a (drv_a[3:0]), + .drv_e (drv_e[3:0])); + Test2 test2 (/*AUTOINST*/ + // Outputs + .match2 (match2[8:0]), + // Inputs + .drv_a (drv_a[3:0]), + .drv_e (drv_e[3:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {39'h0, match2, 7'h0, match1}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n",$time, cyc, crc, match1, match2, drv_e,drv_a,drv_b); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test1 + ( + input wire [3:0] drv_a, + input wire [3:0] drv_e, + output wire [8:0] match1 + ); + + wire [2:1] drv_all; + bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); + +`ifdef VERILATOR + // At present Verilator only allows comparisons with Zs + assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11); + assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11); + assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11); + assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11); +`else + assign match1[0] = drv_all === 2'b00; + assign match1[1] = drv_all === 2'b01; + assign match1[2] = drv_all === 2'b10; + assign match1[3] = drv_all === 2'b11; +`endif + assign match1[4] = drv_all === 2'bz0; + assign match1[5] = drv_all === 2'bz1; + assign match1[6] = drv_all === 2'bzz; + assign match1[7] = drv_all === 2'b0z; + assign match1[8] = drv_all === 2'b1z; +endmodule + +module Test2 + ( + input wire [3:0] drv_a, + input wire [3:0] drv_e, + output wire [8:0] match2 + ); + + wire [2:1] drv_all; + bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); + +`ifdef VERILATOR + assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11); + assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11); + assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11); + assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11); +`else + assign match2[0] = drv_all !== 2'b00; + assign match2[1] = drv_all !== 2'b01; + assign match2[2] = drv_all !== 2'b10; + assign match2[3] = drv_all !== 2'b11; +`endif + assign match2[4] = drv_all !== 2'bz0; + assign match2[5] = drv_all !== 2'bz1; + assign match2[6] = drv_all !== 2'bzz; + assign match2[7] = drv_all !== 2'b0z; + assign match2[8] = drv_all !== 2'b1z; +endmodule diff --git a/test/cli/verilog/t_tri_inz.v b/test/cli/verilog/t_tri_inz.v new file mode 100644 index 00000000..f26fce1c --- /dev/null +++ b/test/cli/verilog/t_tri_inz.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module top + (input d, + output ext0, + output ext1, + output extx, + output extz); + + assign ext0 = (d === 1'b0); + assign ext1 = (d === 1'b1); + assign extx = (d === 1'bx); + assign extz = (d === 1'bz); +endmodule diff --git a/test/cli/verilog/t_tri_pull01.v b/test/cli/verilog/t_tri_pull01.v new file mode 100644 index 00000000..2d1248a9 --- /dev/null +++ b/test/cli/verilog/t_tri_pull01.v @@ -0,0 +1,94 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Test: + tri t; + bufif1 (t, crc[1], cyc[1:0]==2'b00); + bufif1 (t, crc[2], cyc[1:0]==2'b10); + + tri0 t0; + bufif1 (t0, crc[1], cyc[1:0]==2'b00); + bufif1 (t0, crc[2], cyc[1:0]==2'b10); + + tri1 t1; + bufif1 (t1, crc[1], cyc[1:0]==2'b00); + bufif1 (t1, crc[2], cyc[1:0]==2'b10); + + tri t2; + t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00)); + bufif1 (t2, crc[2], cyc[1:0]==2'b10); + + tri t3; + t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00)); + bufif1 (t3, crc[2], cyc[1:0]==2'b10); + + wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h04f91df71371e950 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module t_tri2 (/*AUTOARG*/ + // Outputs + t2, + // Inputs + d, oe + ); + output t2; + input d; + input oe; + tri1 t2; + bufif1 (t2, d, oe); +endmodule + +module t_tri3 (/*AUTOARG*/ + // Outputs + t3, + // Inputs + d, oe + ); + output tri1 t3; + input d; + input oe; + bufif1 (t3, d, oe); +endmodule diff --git a/test/cli/verilog/t_tri_select.v b/test/cli/verilog/t_tri_select.v new file mode 100644 index 00000000..a270dd92 --- /dev/null +++ b/test/cli/verilog/t_tri_select.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 + +`define WIDTH 2 + +module top ( + input OE1, + input OE2, + input [`WIDTH-1:0] A1, + input [`WIDTH-1:0] A2, + output [`WIDTH-1:0] Y1, + output [`WIDTH-1:0] Y2, + output [`WIDTH-1:0] Y3, + output [`WIDTH**2-1:0] W); + + assign W[A1] = (OE2) ? A2[0] : 1'bz; + assign W[A2] = (OE1) ? A2[1] : 1'bz; + + // have 2 different 'chips' drive the PAD to act like a bi-directional bus + wire [`WIDTH-1:0] PAD; + io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD)); + io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD)); + + assign Y3 = PAD; + + pullup p1(PAD); +// pulldown p1(PAD); + + + wire [5:0] fill = { 4'b0, A1 }; + +endmodule + +module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD); + io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD)); +endmodule + +module io (input OE, input I, output O, inout PAD); + assign O = PAD; + assign PAD = OE ? I : 1'bz; +endmodule diff --git a/test/cli/verilog/t_type.v b/test/cli/verilog/t_type.v new file mode 100644 index 00000000..ce40dee7 --- /dev/null +++ b/test/cli/verilog/t_type.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/); + + real x; + real y; + var type(x+y) z; + + initial begin + x = 1.2; + y = 2.3; + z = x + y; + if (z != (1.2+2.3)) $stop; + z = type(z)'(22); + if (z != 22.0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_type_param.v b/test/cli/verilog/t_type_param.v new file mode 100644 index 00000000..891f7da2 --- /dev/null +++ b/test/cli/verilog/t_type_param.v @@ -0,0 +1,112 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 + +module foo + #(parameter type bar = logic) + (output int bar_size); + + localparam baz = $bits(bar); + + assign bar_size = baz; +endmodule + +module foo_wrapper + #(parameter bar_bits = 9) + (output int bar_size); + + foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size)); + +endmodule + +module t(); + logic [7:0] qux1; + int bar_size1; + + foo #(.bar (logic [ $bits(qux1) - 1 : 0])) + foo_inst1 (.bar_size (bar_size1)); + + logic [7:0] qux2; + int bar_size2; + + foo #(.bar (logic [ $bits(qux2) - 1 : 0])) + foo_inst2 (.bar_size (bar_size2)); + + logic [7:0] qux3; + int bar_size3; + + foo #(.bar (logic [ $bits(qux3) - 1 : 0])) + foo_inst3 (.bar_size (bar_size3)); + + localparam bar_bits = 13; + int bar_size_wrapper; + + foo_wrapper #(.bar_bits (bar_bits)) + foo_wrapper_inst (.bar_size (bar_size_wrapper)); + + initial begin + if ($bits(qux1) != foo_inst1.baz) begin + $display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)", + $bits(qux1), foo_inst1.baz); + $stop(); + end + if ($bits(qux2) != foo_inst2.baz) begin + $display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)", + $bits(qux2), foo_inst2.baz); + $stop(); + end + if ($bits(qux3) != foo_inst3.baz) begin + $display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)", + $bits(qux3), foo_inst3.baz); + $stop(); + end + if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin + $display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)", + bar_bits, foo_wrapper_inst.foo_inst.baz); + $stop(); + end + if (bar_size1 != $bits(qux1)) begin + $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", + bar_size1, $bits(qux1)); + $stop(); + end + if (bar_size2 != $bits(qux2)) begin + $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", + bar_size2, $bits(qux2)); + $stop(); + end + if (bar_size3 != $bits(qux3)) begin + $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", + bar_size3, $bits(qux3)); + $stop(); + end + if (bar_size_wrapper != bar_bits) begin + $display("%m: bar_size_wrapper != bar_bits (%0d, %0d)", + bar_size_wrapper, bar_bits); + $stop(); + end + end + + genvar m; + generate + for (m = 1; m <= 8; m+=1) begin : gen_m + initial begin + if (m != foo_inst.baz) begin + $display("%m: m != bits of foo_inst.baz (%0d, %0d)", + m, foo_inst.baz); + $stop(); + end + end + + foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ()); + end + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_unbounded.v b/test/cli/verilog/t_unbounded.v new file mode 100644 index 00000000..a8b6d3bb --- /dev/null +++ b/test/cli/verilog/t_unbounded.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(); + + localparam UNB = $; + localparam int UNB2 = $; + localparam SIX = 6; + + initial begin + if ($bits($isunbounded(0)) !== 1) $stop; + if ($isunbounded(0) !== 1'b0) $stop; + if ($isunbounded(SIX) !== 0) $stop; + if ($isunbounded($) !== 1) $stop; + if ($isunbounded(UNB) !== 1) $stop; + if ($isunbounded(UNB2) !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_unconnected.v b/test/cli/verilog/t_unconnected.v new file mode 100644 index 00000000..4cce7be4 --- /dev/null +++ b/test/cli/verilog/t_unconnected.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire o_n; + wire o_0; + wire o_1; + + // verilator lint_off PINMISSING + sub_0 sub_0(.o_0); + sub_1 sub_1(.o_1); + sub_n sub_n(.o_n); + // verilator lint_on PINMISSING + + always @ (posedge clk) begin + if (o_0 !== 1'b0) $stop; + if (o_1 !== 1'b1) $stop; + //4-state if (o_n !== 1'bz) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +`unconnected_drive pull0 +module sub_0 (input i, output wire o_0); + assign o_0 = i; +endmodule + +`unconnected_drive pull1 +module sub_1 (input i, output wire o_1); + assign o_1 = i; +endmodule + +`nounconnected_drive +module sub_n (input i, output wire o_n); + assign o_n = i; +endmodule diff --git a/test/cli/verilog/t_uniqueif.v b/test/cli/verilog/t_uniqueif.v new file mode 100644 index 00000000..137b860f --- /dev/null +++ b/test/cli/verilog/t_uniqueif.v @@ -0,0 +1,112 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc=1; + integer a, b, c, d, e, f, g, h, i, j, k, l; + + always @ (posedge clk) begin + cyc <= cyc + 1; + + //==================== + // Positive test cases + //==================== + + // Single if, which is untrue sometimes + unique0 if (cyc > 5) + a <= 17; + + // single if with else + unique0 if (cyc < 3) + b <= 17; + else + b <= 19; + + // multi if, some cases may not be true + unique0 if (cyc < 3) + c <= 17; + else if (cyc > 3) + c <= 19; + + // multi if with else, else clause hit in some cases + unique0 if (cyc < 3) + d <= 17; + else if (cyc > 3) + d <= 19; + else + d <= 21; + + // single if with else + unique if (cyc < 3) + f <= 17; + else + f <= 19; + + // multi if + unique if (cyc < 3) + g <= 17; + else if (cyc >= 3) + g <= 19; + + // multi if with else, else clause hit in some cases + unique if (cyc < 3) + h <= 17; + else if (cyc > 3) + h <= 19; + else + h <= 21; + + //==================== + // Negative test cases + //==================== +`ifdef FAILING_ASSERTION1 + $display("testing fail 1: %d", cyc); + // multi if, multiple cases true + unique0 if (cyc < 3) + i <= 17; + else if (cyc < 5) + i <= 19; +`endif + +`ifdef FAILING_ASSERTION2 + // multi if, multiple cases true + unique if (cyc < 3) + j <= 17; + else if (cyc < 5) + j <= 19; +`endif + +`ifdef FAILING_ASSERTION3 + // multi if, no cases true + unique if (cyc > 1000) + k <= 17; + else if (cyc > 2000) + k <= 19; +`endif + +`ifdef FAILING_ASSERTION4 + // Single if, which is untrue sometimes. + // The LRM states: "A software tool shall also issue an error if it determines that no condition' + // is true, or it is possible that no condition is true, and the final if does not have a + // corresponding else." In this case, the final if is the only if, but I think the clause + // still applies. + unique if (cyc > 5) + l <= 17; +`endif + + + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_unopt_array.v b/test/cli/verilog/t_unopt_array.v new file mode 100644 index 00000000..1158c8bb --- /dev/null +++ b/test/cli/verilog/t_unopt_array.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h458c2de282e30f8b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output wire [31:0] out; + + reg [31:0] stage [3:0]; + + genvar g; + + generate + for (g=0; g<4; g++) begin + always_comb begin + if (g==0) stage[g] = in; + else stage[g] = {stage[g-1][30:0],1'b1}; + end + end + endgenerate + + assign out = stage[3]; +endmodule diff --git a/test/cli/verilog/t_unopt_combo.v b/test/cli/verilog/t_unopt_combo.v new file mode 100644 index 00000000..c4d7e6d1 --- /dev/null +++ b/test/cli/verilog/t_unopt_combo.v @@ -0,0 +1,142 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] b; // From file of file.v + wire [31:0] c; // From file of file.v + wire [31:0] d; // From file of file.v + // End of automatics + + file file (/*AUTOINST*/ + // Outputs + .b (b[31:0]), + .c (c[31:0]), + .d (d[31:0]), + // Inputs + .crc (crc[31:0])); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {b, d} + ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h649ee1713d624dd9) $stop; + $finish; + end + end + +endmodule + +module file (/*AUTOARG*/ + // Outputs + b, c, d, + // Inputs + crc + ); + + input [31:0] crc; +`ifdef ISOLATE + output reg [31:0] b /* verilator isolate_assignments*/; +`else + output reg [31:0] b; +`endif + + output reg [31:0] c; + output reg [31:0] d; + + always @* begin + // Note that while c and b depend on crc, b doesn't depend on c. + casez (crc[3:0]) + 4'b??01: begin + b = {crc[15:0],get_31_16(crc)}; + d = c; + end + 4'b??00: begin + b = {crc[15:0],~crc[31:16]}; + d = {crc[15:0],~c[31:16]}; + end + default: begin + set_b_d(crc, c); + end + endcase + end + +`ifdef ISOLATE + function [31:16] get_31_16 /* verilator isolate_assignments*/; + input [31:0] t_crc /* verilator isolate_assignments*/; + get_31_16 = t_crc[31:16]; + endfunction +`else + function [31:16] get_31_16; + input [31:0] t_crc; + get_31_16 = t_crc[31:16]; + endfunction +`endif + + task set_b_d; +`ifdef ISOLATE + input [31:0] t_crc /* verilator isolate_assignments*/; + input [31:0] t_c /* verilator isolate_assignments*/; +`else + input [31:0] t_crc; + input [31:0] t_c; +`endif + begin + b = {t_crc[31:16],~t_crc[23:8]}; + d = {t_crc[31:16], ~t_c[23:8]}; + end + endtask + + always @* begin + // Any complicated equation we can't optimize + casez (crc[3:0]) + 4'b00??: begin + c = {b[29:0],2'b11}; + end + 4'b01??: begin + c = {b[30:1],2'b01}; + end + 4'b10??: begin + c = {b[31:2],2'b10}; + end + 4'b11??: begin + c = {b[31:2],2'b00}; + end + endcase + end + +endmodule diff --git a/test/cli/verilog/t_unopt_converge.v b/test/cli/verilog/t_unopt_converge.v new file mode 100644 index 00000000..702c0f32 --- /dev/null +++ b/test/cli/verilog/t_unopt_converge.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + x, + // Inputs + clk + ); + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + input clk; + output x; // Avoid eliminating x + + reg x; + always @* begin + x = ~x; + end + +endmodule diff --git a/test/cli/verilog/t_unopt_converge_initial.v b/test/cli/verilog/t_unopt_converge_initial.v new file mode 100644 index 00000000..abfc6f32 --- /dev/null +++ b/test/cli/verilog/t_unopt_converge_initial.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + x, + // Inputs + clk + ); + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + input clk; + output [31:0] x; // Avoid eliminating x + + reg [31:0] x; + always @* begin + x = x ^ $random; + end + +endmodule diff --git a/test/cli/verilog/t_unoptflat_simple.v b/test/cli/verilog/t_unoptflat_simple.v new file mode 100644 index 00000000..7c9f63f8 --- /dev/null +++ b/test/cli/verilog/t_unoptflat_simple.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Simple demonstration of an UNOPTFLAT combinatorial loop, using just 2 bits. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [1:0] x = { x[0], clk }; + + initial begin + x = 0; + end + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("x = %x\n", x); +`endif + + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_unoptflat_simple_2.v b/test/cli/verilog/t_unoptflat_simple_2.v new file mode 100644 index 00000000..549f69b4 --- /dev/null +++ b/test/cli/verilog/t_unoptflat_simple_2.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [2:0] x; + + assign x[1:0] = { x[0], clk }; + assign x[2:1] = x[1:0]; + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("x = %x\n", x); +`endif + + if (x[2] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule // t diff --git a/test/cli/verilog/t_unoptflat_simple_3.v b/test/cli/verilog/t_unoptflat_simple_3.v new file mode 100644 index 00000000..09c33e22 --- /dev/null +++ b/test/cli/verilog/t_unoptflat_simple_3.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping +// through 2 sub-modules. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [2:0] x; + + initial begin + x = 3'b000; + end + + test1 test1i ( .clk (clk), + .xvecin (x[1:0]), + .xvecout (x[2:1])); + + test2 test2i ( .clk (clk), + .xvecin (x[2:1]), + .xvecout (x[1:0])); + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write("x = %x\n", x); +`endif + + if (x[1] != 0) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule // t + + +module test1 + (/*AUTOARG*/ + // Inputs + clk, + xvecin, + // Outputs + xvecout + ); + + input clk; + input wire [1:0] xvecin; + + output wire [1:0] xvecout; + + assign xvecout = {xvecin[0], clk}; + +endmodule // test + + +module test2 + (/*AUTOARG*/ + // Inputs + clk, + xvecin, + // Outputs + xvecout + ); + + input clk; + input wire [1:0] xvecin; + + output wire [1:0] xvecout; + + assign xvecout = {clk, xvecin[1]}; + +endmodule // test diff --git a/test/cli/verilog/t_unpacked_slice.v b/test/cli/verilog/t_unpacked_slice.v new file mode 100644 index 00000000..ea76566d --- /dev/null +++ b/test/cli/verilog/t_unpacked_slice.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/); + + parameter int sliceddn[7:0] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; + parameter int slicedup[0:7] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; + int alldn[7:0]; + int allup[0:7]; + int twodn[1:0]; + int twoup[0:1]; + + initial begin + `checkh(sliceddn[7], 'h100); + alldn[7:0] = sliceddn[7:0]; + `checkh(alldn[7], 'h100); + alldn[7:0] = sliceddn[0 +: 8]; // down: lsb/lo +: width + `checkh(alldn[7], 'h100); + alldn[7:0] = sliceddn[7 -: 8]; // down: msb/hi -: width + `checkh(alldn[7], 'h100); + twodn[1:0] = sliceddn[6:5]; + `checkh(twodn[1], 'h101); + `checkh(twodn[0], 'h102); + twodn[1:0] = sliceddn[4 +: 2]; + `checkh(twodn[1], 'h102); + `checkh(twodn[0], 'h103); + twodn[1:0] = sliceddn[4 -: 2]; + `checkh(twodn[1], 'h103); + `checkh(twodn[0], 'h104); + + `checkh(slicedup[7], 'h107); + allup[0:7] = slicedup[0:7]; + `checkh(alldn[7], 'h100); + allup[0:7] = slicedup[0 +: 8]; // up: msb/lo +: width + `checkh(alldn[7], 'h100); + allup[0:7] = slicedup[7 -: 8]; // up: lsb/hi -: width + `checkh(alldn[7], 'h100); + twoup[0:1] = slicedup[5:6]; + `checkh(twoup[1], 'h106); + `checkh(twoup[0], 'h105); + twoup[0:1] = slicedup[4 +: 2]; + `checkh(twoup[1], 'h105); + `checkh(twoup[0], 'h104); + twoup[0:1] = slicedup[4 -: 2]; + `checkh(twoup[1], 'h104); + `checkh(twoup[0], 'h103); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_unroll_forfor.v b/test/cli/verilog/t_unroll_forfor.v new file mode 100644 index 00000000..a37ad75e --- /dev/null +++ b/test/cli/verilog/t_unroll_forfor.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This files is used to generated the following error: +// %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Jan Egil Ruud. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk, in + ); + input clk; + input [71:0] in; + + reg [71:0] in_tmp; + + localparam [71:0] TEST_PARAM = {72{1'b0}}; + + // Test loop + always @* + begin: testmap + byte i, j; + // bug1044 + for ( i = 0; i < 9; i = i + 1 ) + // verilator lint_off WIDTH + for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin + in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; + end + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_unroll_genf.v b/test/cli/verilog/t_unroll_genf.v new file mode 100644 index 00000000..70d4852c --- /dev/null +++ b/test/cli/verilog/t_unroll_genf.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +//bug830 +module sub(); +endmodule + +function integer cdiv(input integer x); + begin + cdiv = 10; + end +endfunction + +module t (/*AUTOARG*/); + + genvar j; + generate + for (j = 0; j < cdiv(10); j=j+1) + sub sub(); + endgenerate + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_vams_basic.v b/test/cli/verilog/t_vams_basic.v new file mode 100644 index 00000000..c658d64e --- /dev/null +++ b/test/cli/verilog/t_vams_basic.v @@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`begin_keywords "VAMS-2.3" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + task check (integer line, real got, real expec); + real delta; + delta = got-expec; + if (delta > 0.001) begin + $display("Line%d: Got %g Exp %g\n", line, got, expec); + $stop; + end + endtask + + wreal wr; + assign wr = 1.1; + + sub sub (.*); + + initial begin + check(`__LINE__, sqrt(2.0) , 1.414); + check(`__LINE__, pow(2.0,2.0) , 4.0); + check(`__LINE__, ln(2.0) , 0.693147); + check(`__LINE__, log(2.0) , 0.30103); + check(`__LINE__, floor(2.5) , 2.0); + check(`__LINE__, exp(2.0) , 7.38906); + check(`__LINE__, ceil(2.5) , 3.0); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module sub ( + input wreal wr + ); + initial begin + if (wr != 1.1) $stop; + end +endmodule diff --git a/test/cli/verilog/t_var_assign_landr.v b/test/cli/verilog/t_var_assign_landr.v new file mode 100644 index 00000000..4713eea8 --- /dev/null +++ b/test/cli/verilog/t_var_assign_landr.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [255:0] sum; + + // Take CRC data and apply to testblock inputs + wire [127:0] in = {~crc[63:0], crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [127:0] o1; // From test of Test.v + wire [127:0] o2; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .o1 (o1[127:0]), + .o2 (o2[127:0]), + // Inputs + .in (in[127:0])); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x %x\n",$time, cyc, crc, o1, o2); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + o1, o2, + // Inputs + in + ); + + input [127:0] in; + output logic [127:0] o1; + output logic [127:0] o2; + + always_comb begin: b_test + logic [127:0] tmpp; + logic [127:0] tmp; + tmp = '0; + tmpp = '0; + + tmp[63:0] = in[63:0]; + tmpp[63:0] = in[63:0]; + + tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; + tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; + + o1 = tmp; + o2 = tmpp; + end + +endmodule diff --git a/test/cli/verilog/t_var_const.v b/test/cli/verilog/t_var_const.v new file mode 100644 index 00000000..c8ff9be0 --- /dev/null +++ b/test/cli/verilog/t_var_const.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + const logic [2:0] five = 3'd5; + + const logic unsigned [31:0] var_const = 22; + logic [7:0] res_const; + assign res_const = var_const[7:0]; // bug693 + + always @ (posedge clk) begin + if (five !== 3'd5) $stop; + if (res_const !== 8'd22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_var_dup2.v b/test/cli/verilog/t_var_dup2.v new file mode 100644 index 00000000..d2b18006 --- /dev/null +++ b/test/cli/verilog/t_var_dup2.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Legal with ANSI Verilog 2001 style ports +module t + ( + output wire ok_ow, + output reg ok_or); + + wire ok_o_w; + reg ok_o_r; +endmodule diff --git a/test/cli/verilog/t_var_dup3.v b/test/cli/verilog/t_var_dup3.v new file mode 100644 index 00000000..812c9274 --- /dev/null +++ b/test/cli/verilog/t_var_dup3.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Legal with Verilog 1995 style ports + +module t + (/*AUTOARG*/ + // Outputs + ok_o_w, ok_o_r, ok_o_ra, ok_or, ok_ow, ok_owa + ); + + output ok_o_w; + wire ok_o_w; + + output ok_o_r; + reg ok_o_r; + + output [1:0] ok_o_ra; + reg [1:0] ok_o_ra; + + output reg ok_or; + + output wire ok_ow; + + output wire [1:0] ok_owa; +endmodule diff --git a/test/cli/verilog/t_var_in_assign.v b/test/cli/verilog/t_var_in_assign.v new file mode 100644 index 00000000..26377559 --- /dev/null +++ b/test/cli/verilog/t_var_in_assign.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + integer v; + + reg i; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire oa; // From a of a.v + wire oz; // From z of z.v + // End of automatics + + a a (.*); + z z (.*); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz); +`endif + cyc <= cyc + 1; + i <= cyc[0]; + if (cyc==0) begin + v = 3; + if (v !== 3) $stop; + if (assignin(v) !== 2) $stop; + if (v !== 3) $stop; // Make sure V didn't get changed + end + else if (cyc<10) begin + if (cyc==11 && oz!==1'b0) $stop; + if (cyc==12 && oz!==1'b1) $stop; + if (cyc==12 && oa!==1'b1) $stop; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + function integer assignin(input integer i); + i = 2; + assignin = i; + endfunction + +endmodule + +module a (input i, output oa); + // verilator lint_off ASSIGNIN + assign i = 1'b1; + assign oa = i; +endmodule + +module z (input i, output oz); + assign oz = i; +endmodule diff --git a/test/cli/verilog/t_var_init.v b/test/cli/verilog/t_var_init.v new file mode 100644 index 00000000..87f4dfab --- /dev/null +++ b/test/cli/verilog/t_var_init.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + parameter [31:0] p2=2, p3=3; + integer i2=2, i3=3; + reg [31:0] r2=2, r3=3; + wire [31:0] w2=2, w3=3; + + always @ (posedge clk) begin + if (p2 !== 2) $stop; + if (p3 !== 3) $stop; + if (i2 !== 2) $stop; + if (i3 !== 3) $stop; + if (r2 !== 2) $stop; + if (r3 !== 3) $stop; + if (w2 !== 2) $stop; + if (w3 !== 3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_var_life.v b/test/cli/verilog/t_var_life.v new file mode 100644 index 00000000..f8a876eb --- /dev/null +++ b/test/cli/verilog/t_var_life.v @@ -0,0 +1,105 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + // Life analysis checks + reg [15:0] life; + + // Ding case + reg [7:0] din; + reg [15:0] fixin; + always @* begin + fixin = {din[7:0],din[7:0]}; + case (din[1:0]) + 2'b00: begin + fixin = {fixin[14:0], 1'b1}; + if (cyc==101) $display("Prevent ?: optimization a"); + end + 2'b01: begin + fixin = {fixin[13:0], 2'b11}; + if (cyc==101) $display("Prevent ?: optimization b"); + end + 2'b10: begin + fixin = {fixin[12:0], 3'b111}; + if (cyc==101) $display("Prevent ?: optimization c"); + end + 2'b11: begin + fixin = {fixin[11:0], 4'b1111}; + if (cyc==101) $display("Prevent ?: optimization d"); + end + endcase + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==1) begin + life = 16'h8000; // Dropped + life = 16'h0010; // Used below + if (life != 16'h0010) $stop; + // + life = 16'h0020; // Used below + if ($time < 10000) + if (life != 16'h0020) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + if ($time != 0) $stop; // Prevent conversion to ?: + life = 16'h1030; + end + else + life = 16'h0030; + if (life != 16'h0030) $stop; + // + life = 16'h0040; // Not dropped, no else below + if ($time > 100000) + life = 16'h1040; + if (life != 16'h0040) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + life = 16'h1050; + if (life != 0) $stop; // Ignored, as set is first + end + else begin + if ($time > 100010) + life = 16'h1050; + else life = 16'h0050; + end + if (life != 16'h0050) $stop; + end + if (cyc==2) begin + din <= 8'haa; + end + if (cyc==3) begin + din <= 8'hfb; + if (fixin != 16'h5557) $stop; + end + if (cyc==4) begin + din <= 8'h5c; + if (fixin != 16'hbfbf) $stop; + end + if (cyc==5) begin + din <= 8'hed; + if (fixin != 16'hb8b9) $stop; + end + if (cyc==6) begin + if (fixin != 16'hb7b7) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test/cli/verilog/t_var_local.v b/test/cli/verilog/t_var_local.v new file mode 100644 index 00000000..25a112a0 --- /dev/null +++ b/test/cli/verilog/t_var_local.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + integer top; + integer top_assign=1; + + task automatic tsk; + integer task_assign = 1; + if (task_assign != 1) $stop; + task_assign = 2; + if (task_assign != 2) $stop; + endtask + + initial begin + begin : a + integer lower; + integer lower_assign=1; + lower = 1; + top = 1; + if (lower != 1) $stop; + if (lower_assign != 1) $stop; + begin : aa + integer lev2; + lev2 = 1; + lower = 2; + lower_assign = 2; + top = 2; + end + if (lower != 2) $stop; + if (lower_assign != 2) $stop; + end + begin : b + integer lower; + lower = 1; + top = 2; + begin : empty + begin : empty + end + end + end + tsk; + tsk; // Second time to ensure we reinit the initial value + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_var_nonamebegin.v b/test/cli/verilog/t_var_nonamebegin.v new file mode 100644 index 00000000..164e5a3b --- /dev/null +++ b/test/cli/verilog/t_var_nonamebegin.v @@ -0,0 +1,79 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk, reset_l + ); + + input clk; + input reset_l; + + reg inmod; + + generate + if (1) begin + // Traces as genblk1.ingen + integer ingen; + initial $display("ingen: {mod}.genblk1 %m"); + end + endgenerate + + integer rawmod; + + initial begin + begin + integer upa; + begin : d3nameda + // %m='.d3nameda' var=_unnamed#.d3nameda.b1 + integer d3a; + $display("d3a: {mod}.d3nameda %m"); + end + end + end + initial begin + integer b2; + $display("b2: {mod} %m"); + begin : b3named + integer b3n; + $display("b3n: {mod}.b3named: %m"); + end + if (1) begin + integer b3; + $display("b3: {mod} %m"); + if (1) begin + begin + begin + begin + integer b4; + $display("b4: {mod} %m"); + end + end + end + end + else begin + integer b4; + $display("bb %m"); + end + end + else begin + integer b4; + $display("b4 %m"); + end + tsk; + $write("*-* All Finished *-*\n"); + $finish; + end + + task tsk; + integer t1; + $display("t1 {mod}.tsk %m"); + begin + integer t2; + $display("t2 {mod}.tsk %m"); + end + endtask + +endmodule diff --git a/test/cli/verilog/t_var_overcmp.v b/test/cli/verilog/t_var_overcmp.v new file mode 100644 index 00000000..c647e4df --- /dev/null +++ b/test/cli/verilog/t_var_overcmp.v @@ -0,0 +1,146 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, rstn, dval0, dval1, dbgsel_w + ); + + input clk; + input rstn; + input [7:0] dval0; + input [7:0] dval1; + input [7:0] dbgsel_w; + output [7:0] dout; + + wire [7:0] dout = dout0 | dout1; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v + // End of automatics + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + + reg [7:0] dbgsel_msk; + always_comb begin + reg [7:0] mask; + mask = 8'hff; + dbgsel_msk = (dbgsel_w & mask); + end + + reg [7:0] dbgsel; + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel <= 0; + end + else begin + dbgsel <= dbgsel_msk; + end + end + + sub0 sub0 (/*AUTOINST*/ + // Outputs + .dout0 (dout0[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); + sub1 sub1 (/*AUTOINST*/ + // Outputs + .dout1 (dout1[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); + +endmodule + +module sub0 + ( + /*AUTOARG*/ + // Outputs + dout0, + // Inputs + rstn, clk, dval1, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout0; + + reg [7:0] dbgsel_d1r; + + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin + // verilator lint_on WIDTH + dout0 = dval1; + end + else begin + dout0 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule + +module sub1 + ( + /*AUTOARG*/ + // Outputs + dout1, + // Inputs + rstn, clk, dval1, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout1; + + reg [7:0] dbgsel_d1r; + + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin + // verilator lint_on WIDTH + dout1 = dval1; + end + else begin + dout1 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule diff --git a/test/cli/verilog/t_var_overzero.v b/test/cli/verilog/t_var_overzero.v new file mode 100644 index 00000000..f2e6ed04 --- /dev/null +++ b/test/cli/verilog/t_var_overzero.v @@ -0,0 +1,173 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, rstn, dval0, dval1 + ); + + input clk; + input rstn; + output wire [7:0] dout; + + input [7:0] dval0; + input [7:0] dval1; + wire [7:0] dbgsel_w = '0; + + tsub tsub (/*AUTOINST*/ + // Outputs + .dout (dout[7:0]), + // Inputs + .clk (clk), + .rstn (rstn), + .dval0 (dval0[7:0]), + .dval1 (dval1[7:0]), + .dbgsel_w (dbgsel_w[7:0])); + +endmodule + +module tsub (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, rstn, dval0, dval1, dbgsel_w + ); + + input clk; + input rstn; + input [7:0] dval0; + input [7:0] dval1; + input [7:0] dbgsel_w; + output [7:0] dout; + + wire [7:0] dout = dout0 | dout1; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v + // End of automatics + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + + reg [7:0] dbgsel_msk; + always_comb begin + reg [7:0] mask; + mask = 8'hff; + dbgsel_msk = (dbgsel_w & mask); + end + + // TODO this should optimize away, but presently does not because + // V3Gate constifies then doesn't see all other input edges have disappeared + reg [7:0] dbgsel; + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel <= 0; + end + else begin + dbgsel <= dbgsel_msk; + end + end + + sub0 sub0 (/*AUTOINST*/ + // Outputs + .dout0 (dout0[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval0 (dval0[7:0]), + .dbgsel (dbgsel[7:0])); + sub1 sub1 (/*AUTOINST*/ + // Outputs + .dout1 (dout1[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); + +endmodule + +module sub0 + ( + /*AUTOARG*/ + // Outputs + dout0, + // Inputs + rstn, clk, dval0, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval0; + input [7:0] dbgsel; + output reg [7:0] dout0; + + reg [7:0] dbgsel_d1r; + + always_comb begin + // verilator lint_off WIDTH + if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin + // verilator lint_on WIDTH + dout0 = dval0; + end + else begin + dout0 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule + +module sub1 + ( + /*AUTOARG*/ + // Outputs + dout1, + // Inputs + rstn, clk, dval1, dbgsel + ); + + input rstn; + input clk; + input [7:0] dval1; + input [7:0] dbgsel; + output reg [7:0] dout1; + + reg [7:0] dbgsel_d1r; + + always_comb begin + if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin + dout1 = dval1; + end + else begin + dout1 = 0; + end + end + + always @(posedge clk) begin + if ((rstn == 0)) begin + dbgsel_d1r <= 0; + end + else begin + dbgsel_d1r <= dbgsel; + end + end + +endmodule diff --git a/test/cli/verilog/t_var_pinsizes.v b/test/cli/verilog/t_var_pinsizes.v new file mode 100644 index 00000000..22ac179c --- /dev/null +++ b/test/cli/verilog/t_var_pinsizes.v @@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Also check that SystemC is ordering properly +// verilator lint_on IMPERFECTSCH + +module t (/*AUTOARG*/ + // Outputs + o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt, + // Inputs + clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt + ); + + input clk; + + input i1; + input [7:0] i8; + input [15:0] i16; + input [31:0] i32; + input [63:0] i64; + input [64:0] i65; + input [127:0] i128; + input [512:0] i513; + input i1a2 [1:0]; + input [93:0] i94a3 [2:0]; + + output logic o1; + output logic [7:0] o8; + output logic [15:0] o16; + output logic [31:0] o32; + output logic [63:0] o64; + output logic [64:0] o65; + output logic [127:0] o128; + output logic [512:0] o513; + output logic o1a2 [1:0]; + output logic [93:0] o94a3 [2:0]; + + input [0:0] ibv1 /*verilator sc_bv*/; + input [15:0] ibv16 /*verilator sc_bv*/; + input [0:0] ibv1_vlt; + input [15:0] ibv16_vlt; + + output logic [0:0] obv1 /*verilator sc_bv*/; + output logic [15:0] obv16 /*verilator sc_bv*/; + output logic [0:0] obv1_vlt; + output logic [15:0] obv16_vlt; + + always @ (posedge clk) begin + o1 <= i1; + o8 <= i8; + o16 <= i16; + o32 <= i32; + o64 <= i64; + o65 <= i65; + o128 <= i128; + o513 <= i513; + obv1 <= ibv1; + obv16 <= ibv16; + obv1_vlt <= ibv1_vlt; + obv16_vlt <= ibv16_vlt; + o1a2 <= i1a2; + o94a3 <= i94a3; + end + +endmodule diff --git a/test/cli/verilog/t_var_set_link.v b/test/cli/verilog/t_var_set_link.v new file mode 100644 index 00000000..d01f989d --- /dev/null +++ b/test/cli/verilog/t_var_set_link.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + state, + // Inputs + clk + ); + input clk; + + // Gave "Internal Error: V3Broken.cpp:: Broken link in node" + output [1:0] state; + reg [1:0] state = 2'b11; + always @ (posedge clk) begin + state <= state; + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_var_tieout.v b/test/cli/verilog/t_var_tieout.v new file mode 100644 index 00000000..17ecee2e --- /dev/null +++ b/test/cli/verilog/t_var_tieout.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug291 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer out18; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire out1; // From test of Test.v + wire out19; // From test of Test.v + wire out1b; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out1 (out1), + .out18 (out18), + .out1b (out1b), + .out19 (out19)); + + // Test loop + always @ (posedge clk) begin + if (out1 !== 1'b1) $stop; + if (out18 !== 32'h18) $stop; + if (out1b !== 1'b1) $stop; + if (out19 !== 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module Test ( + output wire out1 = 1'b1, + output integer out18 = 32'h18, + output var out1b = 1'b1, + output var logic out19 = 1'b1 + ); +endmodule diff --git a/test/cli/verilog/t_var_types.v b/test/cli/verilog/t_var_types.v new file mode 100644 index 00000000..273ad469 --- /dev/null +++ b/test/cli/verilog/t_var_types.v @@ -0,0 +1,227 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + // IEEE: integer_atom_type + byte d_byte; + shortint d_shortint; + int d_int; + longint d_longint; + integer d_integer; + time d_time; + chandle d_chandle; + + // IEEE: integer_atom_type + bit d_bit; + logic d_logic; + reg d_reg; + + bit [1:0] d_bit2; + logic [1:0] d_logic2; + reg [1:0] d_reg2; + + // IEEE: non_integer_type + //UNSUP shortreal d_shortreal; + real d_real; + realtime d_realtime; + + // Declarations using var + var byte v_b; +`ifndef VCS + var [2:0] v_b3; + var signed [2:0] v_bs; +`endif + + // verilator lint_off WIDTH + localparam p_implicit = {96{1'b1}}; + localparam [89:0] p_explicit = {96{1'b1}}; + localparam byte p_byte = {96{1'b1}}; + localparam shortint p_shortint = {96{1'b1}}; + localparam int p_int = {96{1'b1}}; + localparam longint p_longint = {96{1'b1}}; + localparam integer p_integer = {96{1'b1}}; + localparam reg p_reg = {96{1'b1}}; + localparam bit p_bit = {96{1'b1}}; + localparam logic p_logic = {96{1'b1}}; + localparam reg [0:0] p_reg1 = {96{1'b1}}; + localparam bit [0:0] p_bit1 = {96{1'b1}}; + localparam logic [0:0] p_logic1= {96{1'b1}}; + localparam reg [1:0] p_reg2 = {96{1'b1}}; + localparam bit [1:0] p_bit2 = {96{1'b1}}; + localparam logic [1:0] p_logic2= {96{1'b1}}; + // verilator lint_on WIDTH + + byte v_byte[2]; + shortint v_shortint[2]; + int v_int[2]; + longint v_longint[2]; + integer v_integer[2]; + time v_time[2]; + chandle v_chandle[2]; + bit v_bit[2]; + logic v_logic[2]; + reg v_reg[2]; + real v_real[2]; + realtime v_realtime[2]; + + // We do this in two steps so we can check that initialization inside functions works properly + // verilator lint_off WIDTH + function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction + function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction + function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction + function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction + function int f_int; int lv_int; f_int = lv_int; endfunction + function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction + function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction + function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction + function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction + function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction + function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction + function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction + function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction + function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction + function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction + function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction + function time f_time; time lv_time; f_time = lv_time; endfunction + function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction + // verilator lint_on WIDTH + +`ifdef verilator + // For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default! + `define XINIT 1'b1 + `define ALL_TWOSTATE 1'b1 +`else + `define XINIT 1'bx + `define ALL_TWOSTATE 1'b0 +`endif + +`define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \ + if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ + begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ + name = {96{1'b1}}; \ + if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ + if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ + name = {96{1'bx}}; \ + if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ + begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ + + initial begin + // verilator lint_off WIDTH + // verilator lint_off UNSIGNED + // name b sign twost 0init + `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); + `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); + `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); + `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); + `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); + `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); + // verilator lint_on WIDTH + // verilator lint_on UNSIGNED + + // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles +`ifdef VERILATOR // else indeterminate + if ($bits(d_chandle) !== 64) $stop; +`endif + +`define CHECK_P(name,nbits) \ + if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ + + // name b + `CHECK_P(p_implicit ,96); + `CHECK_P(p_implicit[0] ,1 ); + `CHECK_P(p_explicit ,90); + `CHECK_P(p_explicit[0] ,1 ); + `CHECK_P(p_byte ,8 ); + `CHECK_P(p_byte[0] ,1 ); + `CHECK_P(p_shortint ,16); + `CHECK_P(p_shortint[0] ,1 ); + `CHECK_P(p_int ,32); + `CHECK_P(p_int[0] ,1 ); + `CHECK_P(p_longint ,64); + `CHECK_P(p_longint[0] ,1 ); + `CHECK_P(p_integer ,32); + `CHECK_P(p_integer[0] ,1 ); + `CHECK_P(p_bit ,1 ); + `CHECK_P(p_logic ,1 ); + `CHECK_P(p_reg ,1 ); + `CHECK_P(p_bit1 ,1 ); + `CHECK_P(p_logic1 ,1 ); + `CHECK_P(p_reg1 ,1 ); + `CHECK_P(p_bit1[0] ,1 ); + `CHECK_P(p_logic1[0] ,1 ); + `CHECK_P(p_reg1[0] ,1 ); + `CHECK_P(p_bit2 ,2 ); + `CHECK_P(p_logic2 ,2 ); + `CHECK_P(p_reg2 ,2 ); + +`define CHECK_B(varname,nbits) \ + if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ + + `CHECK_B(v_byte[1] ,8 ); + `CHECK_B(v_shortint[1] ,16); + `CHECK_B(v_int[1] ,32); + `CHECK_B(v_longint[1] ,64); + `CHECK_B(v_integer[1] ,32); + `CHECK_B(v_time[1] ,64); + //`CHECK_B(v_chandle[1] + `CHECK_B(v_bit[1] ,1 ); + `CHECK_B(v_logic[1] ,1 ); + `CHECK_B(v_reg[1] ,1 ); + //`CHECK_B(v_real[1] ,64); // $bits not allowed + //`CHECK_B(v_realtime[1] ,64); // $bits not allowed + +`define CHECK_F(fname,nbits,zeroinit) \ + if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ + + // name b 0init + `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 + `CHECK_F(f_explicit ,90,1'b0); + `CHECK_F(f_byte ,8 ,1'b1); + `CHECK_F(f_shortint ,16,1'b1); + `CHECK_F(f_int ,32,1'b1); + `CHECK_F(f_longint ,64,1'b1); + `CHECK_F(f_integer ,32,1'b0); + `CHECK_F(f_time ,64,1'b0); +`ifdef VERILATOR // else indeterminate + `CHECK_F(f_chandle ,64,1'b0); +`endif + `CHECK_F(f_bit ,1 ,1'b1); + `CHECK_F(f_logic ,1 ,1'b0); + `CHECK_F(f_reg ,1 ,1'b0); + `CHECK_F(f_bit1 ,1 ,1'b1); + `CHECK_F(f_logic1 ,1 ,1'b0); + `CHECK_F(f_reg1 ,1 ,1'b0); + `CHECK_F(f_bit2 ,2 ,1'b1); + `CHECK_F(f_logic2 ,2 ,1'b0); + `CHECK_F(f_reg2 ,2 ,1'b0); + + // For unpacked types we don't want width warnings for unsized numbers that fit + d_byte = 2; + d_shortint= 2; + d_int = 2; + d_longint = 2; + d_integer = 2; + + // Special check + d_time = $time; + if ($time !== d_time) $stop; + + // Null checks + d_chandle = null; + if (d_chandle != null) $stop; + if (d_chandle) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_var_vec_sel.v b/test/cli/verilog/t_var_vec_sel.v new file mode 100644 index 00000000..e55cf45a --- /dev/null +++ b/test/cli/verilog/t_var_vec_sel.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug601 + +module t ( + input clk, + input [3:0] in3, // worky + input [0:0] in2 [3:0], // worky + input in1 [3:0], // no worky + input [1:0] sel, + output reg out1, + output reg out2, + output reg out3 + ); + + always @(posedge clk) begin + out3 <= in3[sel] ? in3[sel] : out3; + out2 <= in2[sel] ? in2[sel] : out2; + out1 <= in1[sel] ? in1[sel] : out1; // breaks + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_var_xref_gen.v b/test/cli/verilog/t_var_xref_gen.v new file mode 100644 index 00000000..cb01b337 --- /dev/null +++ b/test/cli/verilog/t_var_xref_gen.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This is to test the handling of VarXRef when the referenced VAR is +// under a generate construction. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jie Xu and Roland Kruse. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk, addr, res + ); + + input clk; + + input [31:0] addr; + output [15:0] res; + + memory i_mem(.addr(addr),.dout(res)); + + assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0; + +endmodule + + + +module memory(addr, dout); + parameter CM_XROWSIZE = 256; + parameter CM_NUMXROWS = 2; + + input [31:0] addr; + output [15:0] dout; + + generate + genvar g_cx; + for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) + begin: cxrow_inst + reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; + end + endgenerate + + assign dout = cxrow_inst[0].cmem_xrow[addr]; +endmodule diff --git a/test/cli/verilog/t_waiveroutput.v b/test/cli/verilog/t_waiveroutput.v new file mode 100644 index 00000000..c84e9dec --- /dev/null +++ b/test/cli/verilog/t_waiveroutput.v @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t_waiveroutput; + + reg width_warn = 2'b11; // Width warning - must be line 18 +endmodule diff --git a/test/cli/verilog/t_wire_types.v b/test/cli/verilog/t_wire_types.v new file mode 100644 index 00000000..fb67e7a7 --- /dev/null +++ b/test/cli/verilog/t_wire_types.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + // IEEE: integer_atom_type + wire byte w_byte; + wire shortint w_shortint; + wire int w_int; + wire longint w_longint; + wire integer w_integer; + + // IEEE: integer_atom_type + wire bit w_bit; + wire logic w_logic; + + wire bit [1:0] w_bit2; + wire logic [1:0] w_logic2; + + // IEEE: non_integer_type + //UNSUP shortreal w_shortreal; + wire real w_real; + + assign w_byte = 8'h12; + assign w_shortint = 16'h1234; + assign w_int = -123456; + assign w_longint = -1234567; + assign w_integer = -123456; + + assign w_bit = 1'b1; + assign w_logic = 1'b1; + + assign w_bit2 = 2'b10; + assign w_logic2 = 2'b10; + + assign w_real = 3.14; + + always @ (posedge clk) begin + `checkh(w_byte, 8'h12); + `checkh(w_shortint, 16'h1234); + `checkh(w_int, -123456); + `checkh(w_longint, -1234567); + `checkh(w_integer, -123456); + `checkh(w_bit, 1'b1); + `checkh(w_logic, 1'b1); + `checkh(w_bit2, 2'b10); + `checkh(w_logic2, 2'b10); + `checkr(w_real, 3.14); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_x_assign.v b/test/cli/verilog/t_x_assign.v new file mode 100644 index 00000000..dd40e363 --- /dev/null +++ b/test/cli/verilog/t_x_assign.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2020 by Geza Lore. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t_x_assign( + input wire clk, + output reg o +); + always @(posedge clk) begin + if (1'bx) o <= 1'd1; else o <= 1'd0; + end +endmodule