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verilog: fixed silice <ccast> case

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This commit is contained in:
Steven Hugg 2021-07-22 09:27:11 -05:00
parent 6a21b467cf
commit bb818c34f8
1 changed files with 4 additions and 0 deletions
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4
src/common/hdl/hdlwasm.ts
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@ -1018,6 +1018,10 @@ export class HDLModuleWASM implements HDLModuleRunner {
return this.bmod.i64.extend_u(val);
} else if (tsrc.left > 31 && tdst.left <= 31) { // 64 -> 32
return this.bmod.i32.wrap(val);
} else if (tsrc.left < 31 && tdst.left == 31 && tsrc.signed) { // sign extend via shift (silice case)
let inst = this.i3264(tdst);
var shift = inst.const(31 - tsrc.left, 0);
return inst.shr_s(inst.shl(val, shift), shift);
}
throw new HDLError([tsrc, tdst], `cannot cast ${tsrc.left}/${tsrc.signed} to ${tdst.left}/${tdst.signed}`);
}