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fixed verilog tests

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This commit is contained in:
Steven Hugg 2018-07-09 20:58:24 -05:00
parent d6a702b929
commit bbe665bb03
3 changed files with 7 additions and 6 deletions
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7
src/worker/workermain.js
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@ -1062,7 +1062,7 @@ function compileJSASM(asmcode, platform, options, is_inline) {
var main_filename = includes[includes.length-1]; var main_filename = includes[includes.length-1];
var code = '`include "' + main_filename + '"\n'; var code = '`include "' + main_filename + '"\n';
code += "/* module " + top_module + " */\n"; code += "/* module " + top_module + " */\n";
var voutput = compileVerilator({code:code, platform:platform, dependencies:options.dependencies}); // TODO var voutput = compileVerilator({code:code, platform:platform, dependencies:options.dependencies, path:options.path}); // TODO
if (voutput.errors.length) if (voutput.errors.length)
return voutput.errors[0].msg; return voutput.errors[0].msg;
jsasm_module_output = voutput; jsasm_module_output = voutput;
@ -1141,10 +1141,11 @@ function compileVerilator(step) {
}); });
starttime(); starttime();
try { try {
verilator_mod.callMain(["--cc", "-O3", "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod, var args = ["--cc", "-O3", "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod,
"-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat', "-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat',
"--x-assign", "fast", "--noassert", "--pins-bv", "33", "--x-assign", "fast", "--noassert", "--pins-bv", "33",
"--top-module", topmod, step.path]); "--top-module", topmod, step.path]
verilator_mod.callMain(args);
} catch (e) { } catch (e) {
console.log(e); console.log(e);
errors.push({line:0,msg:"Compiler internal error: " + e}); errors.push({line:0,msg:"Compiler internal error: " + e});

2
test/cli/testverilog.js
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@ -36,7 +36,7 @@ function compileVerilator(code, callback, nerrors) {
callback(null, msg); callback(null, msg);
}; };
global.onmessage({ global.onmessage({
data:{code:code, platform:'verilog', tool:'verilator'} data:{code:code, platform:'verilog', tool:'verilator', path:'main.v'}
}); });
} }

4
test/cli/testworker.js
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@ -150,7 +150,7 @@ describe('Worker', function() {
}); });
it('should compile verilog example', function(done) { it('should compile verilog example', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/lfsr.v')); var csource = ab2str(fs.readFileSync('presets/verilog/lfsr.v'));
var msgs = [{code:csource, platform:"verilog", tool:"verilator", dependencies:[]}]; var msgs = [{code:csource, platform:"verilog", tool:"verilator", dependencies:[], path:'main.v'}];
var done2 = function(err, msg) { var done2 = function(err, msg) {
var jscode = msg.output.code; var jscode = msg.output.code;
var fn = new Function(jscode); var fn = new Function(jscode);
@ -167,7 +167,7 @@ describe('Worker', function() {
var code = ab2str(fs.readFileSync('presets/verilog/' + dfile)); var code = ab2str(fs.readFileSync('presets/verilog/' + dfile));
depends.push({filename:dfile, data:code, prefix:"verilog"}); depends.push({filename:dfile, data:code, prefix:"verilog"});
} }
var msgs = [{code:csource, platform:"verilog", tool:"jsasm", dependencies:depends}]; var msgs = [{code:csource, platform:"verilog", tool:"jsasm", dependencies:depends, path:'main.asm'}];
var done2 = function(err, msg) { var done2 = function(err, msg) {
var jscode = msg.output.code; var jscode = msg.output.code;
var fn = new Function(jscode); var fn = new Function(jscode);