fixed verilog inline asm
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@ -46,6 +46,7 @@ TODO:
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- show tool-specific (readonly) include files
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- verilog debugging makes it slow
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- fix VCS mame
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- checkmarks for active window
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WEB WORKER FORMAT
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@ -9,17 +9,19 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg ball_reset;
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// 9-bit ball timers
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reg [8:0] ball_htimer;
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reg [8:0] ball_vtimer;
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// motion codes
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// 4-bit motion codes
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reg [3:0] ball_horiz_move;
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reg [3:0] ball_vert_move;
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// stop codes
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localparam ball_horiz_stop = 4'd12;
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localparam ball_vert_stop = 4'd11;
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// 4-bit stop codes
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localparam ball_horiz_stop = 4'd11;
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localparam ball_vert_stop = 4'd10;
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// 5-bit constants to load into counters
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localparam ball_horiz_prefix = 5'b01100; // 192
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@ -36,11 +38,10 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
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);
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// update horizontal timer
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always @(posedge clk or posedge reset) begin
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if (reset || ball_htimer == 0) begin
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if (reset) // center-ish of screen
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ball_htimer <= {5'b11000, ball_horiz_move};
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else if (ball_vtimer == 0) // nudge ball in horiz. dir
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always @(posedge clk or posedge ball_reset)
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begin
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if (ball_reset || &ball_htimer) begin
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if (ball_reset || &ball_vtimer) // nudge ball in horiz. dir
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ball_htimer <= {ball_horiz_prefix, ball_horiz_move};
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else // reset timer but don't move ball horizontally
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ball_htimer <= {ball_horiz_prefix, ball_horiz_stop};
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@ -49,15 +50,22 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
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end
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// update vertical timer
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always @(posedge hsync or posedge reset)
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always @(posedge hsync or posedge ball_reset)
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begin
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if (reset) // center-ish of screen
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ball_vtimer <= {5'b11000, ball_vert_move};
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else if (ball_vtimer == 0) // reset timer
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if (ball_reset || &ball_vtimer) // reset timer
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ball_vtimer <= {ball_vert_prefix, ball_vert_move};
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else
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ball_vtimer <= ball_vtimer + 1;
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end
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// reset ball position
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always @(posedge clk or posedge reset)
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begin
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if (reset)
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ball_reset <= 1;
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else if (hpos == 128 && vpos == 128)
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ball_reset <= 0;
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end
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// collide with vertical and horizontal boundaries
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wire ball_vert_collide = ball_vgfx && vpos >= 240;
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@ -67,18 +75,18 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
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always @(posedge ball_vert_collide or posedge reset)
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begin
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if (reset)
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ball_vert_move <= 4'd10;
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ball_vert_move <= 4'd9;
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else
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ball_vert_move <= 4'b0110 ^ ball_vert_move; // change dir.
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ball_vert_move <= (4'd9 ^ 4'd11) ^ ball_vert_move; // change dir.
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end
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// horizontal bounce
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always @(posedge ball_horiz_collide or posedge reset)
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begin
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if (reset)
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ball_horiz_move <= 4'd11;
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ball_horiz_move <= 4'd10;
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else
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ball_horiz_move <= 4'b0110 ^ ball_horiz_move; // change dir.
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ball_horiz_move <= (4'd10 ^ 4'd12) ^ ball_horiz_move; // change dir.
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end
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// compute ball display
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@ -119,7 +119,7 @@ function getToolForFilename_6502(fn:string) : string {
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return "dasm"; // .a
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}
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abstract class Base6502Platform extends BaseDebugPlatform {
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export abstract class Base6502Platform extends BaseDebugPlatform {
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newCPU(membus : MemoryBus) {
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var cpu = new jt.M6502();
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@ -284,7 +284,7 @@ function BusProbe(bus : MemoryBus) {
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}
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}
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abstract class BaseZ80Platform extends BaseDebugPlatform {
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export abstract class BaseZ80Platform extends BaseDebugPlatform {
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_cpu;
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probe;
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@ -421,7 +421,7 @@ function getToolForFilename_z80(fn) {
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declare var FS, ENV, Module; // mame emscripten
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// TODO: make class
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var BaseMAMEPlatform = function() {
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export function BaseMAMEPlatform() {
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var self = this;
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@ -1158,17 +1158,18 @@ function compileInlineASM(code, platform, options, errors, asmlines) {
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function compileVerilator(step) {
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loadNative("verilator_bin");
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loadGen("worker/verilator2js");
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var code = step.code;
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var platform = step.platform || 'verilog';
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var errors = [];
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var asmlines = [];
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code = compileInlineASM(code, platform, step, errors, asmlines);
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step.code = compileInlineASM(step.code, platform, step, errors, asmlines);
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var code = step.code;
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var match_fn = makeErrorMatcher(errors, /%(.+?): (.+?:)?(\d+)?[:]?\s*(.+)/i, 3, 4);
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var verilator_mod = verilator_bin({
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instantiateWasm: moduleInstFn('verilator_bin'),
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noInitialRun:true,
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print:print_fn,
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printErr:match_fn,
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//TOTAL_MEMORY:64*1024*1024,
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});
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var topmod = detectTopModuleName(code);
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var FS = verilator_mod['FS'];
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@ -165,6 +165,23 @@ describe('Worker', function() {
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doBuild(msgs, done2, 2782, 0, 0);
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});
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it('should compile verilog inline assembler (JSASM)', function(done) {
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var csource = ab2str(fs.readFileSync('presets/verilog/racing_game_cpu.v'));
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var dependfiles = ["hvsync_generator.v", "sprite_bitmap.v", "sprite_renderer.v", "cpu8.v"];
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var depends = [];
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for (var dfile of dependfiles) {
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var code = ab2str(fs.readFileSync('presets/verilog/' + dfile));
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depends.push({filename:dfile, data:code, prefix:"verilog"});
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}
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var msgs = [{code:csource, platform:"verilog", tool:"verilator", dependencies:depends, path:'racing_game_cpu.v'}];
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var done2 = function(err, msg) {
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var jscode = msg.output.code;
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var fn = new Function(jscode);
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assert.ok(fn);
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done(err, msg);
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};
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doBuild(msgs, done2, 49317, 0, 0);
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});
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it('should compile verilog assembler file (JSASM)', function(done) {
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var csource = ab2str(fs.readFileSync('presets/verilog/test2.asm'));
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var dependfiles = ["hvsync_generator.v", "font_cp437_8x8.v", "ram.v", "tile_renderer.v", "sprite_scanline_renderer.v", "lfsr.v", "sound_generator.v", "cpu16.v", "cpu_platform.v"];
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var depends = [];
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