verilog: worker re-uses memory

test/cli/testverilog.js

@@ -5,6 +5,7 @@ var _path = require('path')
 var _cproc = require('child_process');
 var fs = require('fs');
 var wtu = require('./workertestutils.js');
+var heapdump = require("heapdump");
 
 createTestDOM();
 
@@ -66,6 +67,7 @@ function testPerf(msg) {
 }
 
 function compileVerilator(filename, code, callback, nerrors, depends) {
+    // files come back from worker
     global.postMessage = async function(msg) {
       try {
         if (msg.errors && msg.errors.length) {
@@ -90,6 +92,7 @@ function compileVerilator(filename, code, callback, nerrors, depends) {
         }
       }
     };
+    // send files to worker for build
     try {
       global.onmessage({
           data:{
@@ -116,19 +119,20 @@ function testVerilator(filename, disables, nerrors, depends) {
     console.log(filename);
     //if (depends) testIcarus(filename);
     var csource = ab2str(fs.readFileSync(filename));
+    var header = '';
     for (var i=0; i<(disables||[]).length; i++)
-      csource = "/* verilator lint_off " + disables[i] + " */\n" + csource;
-    compileVerilator(filename, csource, done, nerrors||0, depends);
+      header += "/* verilator lint_off " + disables[i] + " */ ";
+    compileVerilator(filename, header + "\n" + csource, done, nerrors||0, depends);
   });
 }
 
 describe('Verilog Worker', function() {
   
   var files = _fs.readdirSync('test/cli/verilog').filter(fn => fn.endsWith('.v'));
-  files = files.slice(0,80);
+  //files = files.slice(0,75);
   for (var fn of files) {
     testVerilator('test/cli/verilog/' + fn, 
-      ['UNDRIVEN','BLKSEQ','WIDTH','PINCONNECTEMPTY','SYNCASYNCNET','UNOPT','UNOPTFLAT','VARHIDDEN','EOFNEWLINE']
+      ['UNDRIVEN','BLKSEQ','WIDTH','PINCONNECTEMPTY','SYNCASYNCNET','UNOPT','UNOPTFLAT','VARHIDDEN','EOFNEWLINE','ASSIGNDLY','CASEX','SYMRSVDWORD','STMTDLY','PROCASSWIRE']
     );
     global.onmessage({data:{reset:true}});
   }
@@ -146,4 +150,10 @@ describe('Verilog Worker', function() {
   testVerilator('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']);
   testVerilator('presets/verilog/cpu6502.v');
 
+}).afterAll(() => {
+/*
+  heapdump.writeSnapshot((err, filename) => {
+    console.log("Heap dump written to", filename);
+  });
+*/
 });

test/cli/verilog/t_math_div0.v

@@ -1,33 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2020 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-module t(/*AUTOARG*/
-   // Outputs
-   y, d2, m2, d3, m3
-   );
-   output [3:0] y;
-   output [31:0] d2;
-   output [31:0] m2;
-   output [63:0] d3;
-   output [63:0] m3;
-   // bug775
-   // verilator lint_off WIDTH
-   assign y = ((0/0) ? 1 : 2) % 0;
-
-   // bug2460
-   reg [31:0]    b;
-   assign d2 = $signed(32'h80000000) / $signed(b);
-   assign m2 = $signed(32'h80000000) % $signed(b);
-   reg [63:0]    b3;
-   assign d3 = $signed(64'h80000000_00000000) / $signed(b3);
-   assign m3 = $signed(64'h80000000_00000000) % $signed(b3);
-
-   initial begin
-      b = 32'hffffffff;
-      b3 = 64'hffffffff_ffffffff;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
-endmodule

test/cli/verilog/t_order_loop_bad.v

@@ -1,42 +0,0 @@
-// DESCRIPTION: Verilator: Non-cutable edge in loop
-//
-// This code (stripped down from a much larger application) has a loop between
-// the use of ready in the first two always blocks. However it should
-// trivially trigger the $write on the first clk posedge.
-//
-// This is a regression test against issue 513.
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2012 by Jeremy Bennett.
-// SPDX-License-Identifier: CC0-1.0
-
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
-
-   reg   ready;
-
-   initial begin
-      ready = 1'b0;
-   end
-
-   always @(posedge ready) begin
-      if ((ready === 1'b1)) begin
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
-
-   always @(posedge ready) begin
-      if ((ready === 1'b0)) begin
-         ready = 1'b1 ;
-      end
-   end
-
-   always @(posedge clk) begin
-      ready = 1'b1;
-   end
-
-endmodule