From f24213aa1d6b0952f589addba267e0de94e8d25d Mon Sep 17 00:00:00 2001
From: Steven Hugg <hugg@fasterlight.com>
Date: Fri, 2 Mar 2018 21:39:32 -0600
Subject: [PATCH] fixed JSASM cache

---
 presets/verilog/test.asm | 55 ++++++++++++++++++++++++++++++++++++++++
 src/platform/verilog.js  |  1 +
 src/worker/workermain.js |  5 +++-
 3 files changed, 60 insertions(+), 1 deletion(-)
 create mode 100644 presets/verilog/test.asm

diff --git a/presets/verilog/test.asm b/presets/verilog/test.asm
new file mode 100644
index 00000000..10a161be
--- /dev/null
+++ b/presets/verilog/test.asm
@@ -0,0 +1,55 @@
+.arch femto16
+
+.include "hvsync_generator.v"
+.include "font_cp437_8x8.v"
+.include "ram.v"
+.include "tile_renderer.v"
+.include "sprite_scanline_renderer.v"
+.include "lfsr.v"
+.include "sound_generator.v"
+.include "cpu16.v"
+.include "cpu_platform.v"
+.module cpu_platform
+
+.org 0x8000
+.len 1024
+      mov       sp,@$6fff
+      mov       dx,@InitPageTable
+      jsr       dx
+      mov       ax,@$4ffe
+      mov       dx,@ClearTiles
+      jsr       dx
+      mov       dx,@ClearSprites
+      jsr       dx
+      reset
+InitPageTable:
+      mov       ax,@$6000       ; screen buffer
+      mov       bx,@$7e00       ; page table start
+      mov       cx,#32          ; 32 rows
+InitPTLoop:
+      mov       [bx],ax
+      add       ax,#32
+      inc       bx
+      dec       cx
+      bnz       InitPTLoop
+      rts
+ClearTiles:
+      mov       bx,@$6000
+      mov       cx,@$390
+ClearLoop:
+        mov     [bx],ax
+        inc     bx
+        dec     cx
+        bnz     ClearLoop
+      rts
+ClearSprites:
+        mov     bx,@$7f00
+        mov     ax,#0
+        mov     cx,#$40
+ClearSLoop:
+        mov     ax,[bx]
+        add     ax,@$101
+        mov     [bx],ax
+        inc     bx
+        dec     cx
+        bnz     ClearSLoop
diff --git a/src/platform/verilog.js b/src/platform/verilog.js
index 4e993179..6760a3a0 100644
--- a/src/platform/verilog.js
+++ b/src/platform/verilog.js
@@ -25,6 +25,7 @@ var VERILOG_PRESETS = [
   {id:'sprite_scanline_renderer.v', name:'Sprite Scanline Renderer'},
   {id:'cpu16.v', name:'16-Bit CPU'},
   {id:'cpu_platform.v', name:'CPU Platform'},
+  {id:'test.asm', name:'Test ASM'},
 ];
 
 var VERILOG_KEYCODE_MAP = makeKeycodeMap([
diff --git a/src/worker/workermain.js b/src/worker/workermain.js
index 7e6bcff6..81dc8351 100644
--- a/src/worker/workermain.js
+++ b/src/worker/workermain.js
@@ -1141,11 +1141,14 @@ function compileJSASM(asmcode, platform, options, is_inline) {
     filename = filename.substr(1, filename.length-2);
     includes.push(filename);
   };
+  var loaded_module = false;
   asm.loadModule = function(top_module) {
     // TODO: cache module
     // compile last file in list
+    loaded_module = true;
     var key = top_module + '/' + includes;
     if (key != jsasm_module_key) {
+      jsasm_module_key = key;
       jsasm_module_top = top_module;
       var main_filename = includes[includes.length-1];
       var code = '`include "' + main_filename + '"\n';
@@ -1157,7 +1160,7 @@ function compileJSASM(asmcode, platform, options, is_inline) {
     }
   }
   var result = asm.assembleFile(asmcode);
-  if (jsasm_module_output) {
+  if (loaded_module && jsasm_module_output) {
     var asmout = result.output;
     result.output = jsasm_module_output.output;
     result.output.program_rom = asmout;