8 Commits

Author	SHA1	Message	Date
Steven Hugg	706a24c96a	updated presets, changed array syntax, ice40 fpga examples	2018-10-08 20:38:39 -04:00
Steven Hugg	716205a2b1	fixed unit tests	2018-10-03 15:06:48 -04:00
Steven Hugg	684a642ad0	fixed multiplex issue in racing_game	2018-10-01 22:03:44 -04:00
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	2dbc60aa2e	updated presets; verilog code dup detect; need to handle local/ include files somehow	2018-07-31 23:03:53 -04:00
Steven Hugg	4ea23e21f2	fixed verilog local paths	2018-07-22 22:26:03 -04:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00