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194 Commits 3 Branches 31 Tags 162 MiB
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4 Commits

Author SHA1 Message Date
Steven Hugg
8f1563f88e sync vs async RAM 2018-02-28 09:26:37 -06:00
Steven Hugg
b2beb2670c more Verilog code; inline asm for depends; fixed tank 2018-02-25 10:34:27 -06:00
Steven Hugg
20ddb8a11f moved around ALU ops, 16-bit cpu, reg/wire 2018-02-21 11:03:38 -06:00
Steven Hugg
1790ca1747 updated verilog presets and test makefile 2018-02-16 23:33:29 -06:00