7 Commits

Author	SHA1	Message	Date
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00
Steven Hugg	11992645d6	more presets	2018-02-09 00:11:36 -06:00
Steven Hugg	f0f6783f6b	more verilog presets	2018-02-03 20:37:12 -06:00