5 Commits

Author	SHA1	Message	Date
Steven Hugg	bd8c4da2d6	verilog presets; early exit from jsasm errors	2018-09-08 19:14:51 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	11992645d6	more presets	2018-02-09 00:11:36 -06:00
Steven Hugg	bafc23cb5b	tank, pixel edit > 8 bits	2017-12-04 16:40:10 -05:00