98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
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/*
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Multiple screen splits with the MMC3 mapper using IRQs.
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The main loop updates the scroll counters continuously.
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When a IRQ fires, we change the X scroll register, setting
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it immediately via the PPU struct.
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The NMI and IRQ use the same callback function.
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*/
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// bank-switching configuration
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#define NES_MAPPER 4 // Mapper 4 (MMC3)
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#define NES_PRG_BANKS 4 // # of 16KB PRG banks
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#define NES_CHR_BANKS 1 // # of 8KB CHR banks
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#include <peekpoke.h>
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#include <string.h>
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#include <nes.h>
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#include "neslib.h"
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// link the pattern table into CHR ROM
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//#link "chr_generic.s"
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// "strobe" means "write any value"
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#define STROBE(addr) __asm__ ("sta %w", addr)
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#define MMC3_IRQ_SET_VALUE(n) POKE(0xc000, (n));
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#define MMC3_IRQ_RELOAD() STROBE(0xc001)
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#define MMC3_IRQ_DISABLE() STROBE(0xe000)
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#define MMC3_IRQ_ENABLE() STROBE(0xe001)
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void draw_text(word addr, const char* text) {
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vram_adr(addr);
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vram_write(text, strlen(text));
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}
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word counters[128];
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byte irqcount = 0;
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void __fastcall__ irq_nmi_callback(void) {
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// check high bit of A to see if this is an IRQ
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if (__A__ & 0x80) {
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// it's an IRQ from the MMC3 mapper
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// change PPU scroll registers
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PPU.scroll = counters[irqcount & 0x7f] >> 8;
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PPU.scroll = 0;
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// advance to next scroll value
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++irqcount;
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// acknowledge interrupt
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MMC3_IRQ_DISABLE();
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MMC3_IRQ_ENABLE();
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} else {
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// this is a NMI
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// reload IRQ counter
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MMC3_IRQ_RELOAD();
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// reset scroll counter
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irqcount = 0;
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}
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}
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void main(void)
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{
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// More accurate NES emulators simulate the mapper's
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// monitoring of the A12 line, so the background and
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// sprite pattern tables must be different.
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// https://forums.nesdev.com/viewtopic.php?f=2&t=19686#p257380
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set_ppu_ctrl_var(get_ppu_ctrl_var() | 0x08);
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// Enable Work RAM
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POKE(0xA001, 0x80);
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// Mirroring - horizontal
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POKE(0xA000, 0x01);
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// set up MMC3 IRQs every 8 scanlines
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MMC3_IRQ_SET_VALUE(7);
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MMC3_IRQ_RELOAD();
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MMC3_IRQ_ENABLE();
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// enable CPU IRQ
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__asm__ ("cli");
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// set IRQ callback
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nmi_set_callback(irq_nmi_callback);
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// set palette colors
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pal_col(1,0x04);
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pal_col(2,0x20);
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pal_col(3,0x30);
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// fill vram
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vram_adr(NTADR_A(0,0));
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vram_fill('A', 32*28);
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// turn on PPU/interrupts
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ppu_on_all();
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// loop forever, updating each counter at a different rate
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while(1) {
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byte i;
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for (i=0; i<128; i++) {
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counters[i] += i*16;
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}
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ppu_wait_frame();
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}
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}
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