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40 lines
724 B
Verilog
40 lines
724 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] cyc; initial cyc=0;
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reg set_in_task;
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always @ (posedge clk) begin
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if (cyc == 8'd0) begin
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cyc <= 8'd1;
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set_in_task <= 0;
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end
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if (cyc == 8'd1) begin
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cyc <= 8'h2;
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ttask;
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end
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if (cyc == 8'd2) begin
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if (!set_in_task) $stop;
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cyc <= 8'hf;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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task ttask;
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begin
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set_in_task <= 1'b1;
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end
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endtask
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endmodule
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