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37 lines
708 B
Verilog
37 lines
708 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Sean Moore.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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rec rec ();
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endmodule
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module rec;
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parameter DEPTH = 1;
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generate
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if (DEPTH==1) begin
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rec #(.DEPTH(DEPTH+1)) sub;
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end
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else if (DEPTH==2) begin
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rec #(.DEPTH(DEPTH+1)) subb;
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end
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else if (DEPTH==3) begin
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bottom #(.DEPTH(DEPTH+1)) bot;
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end
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endgenerate
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endmodule
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module bottom;
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parameter DEPTH = 1;
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initial begin
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if (DEPTH!=4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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