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14 lines
339 B
Verilog
14 lines
339 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_multitop1s;
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initial $display("In '%m'");
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endmodule
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module in_subfile;
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initial $display("In '%m'");
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endmodule
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