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40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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sub #(.IDX(0), .CHK(10)) i0;
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sub #(.IDX(2), .CHK(12)) i2;
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sub #(.IDX(7), .CHK(17)) i7;
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub ();
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function integer get_element;
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input integer index;
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input integer array_arg[7:0];
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get_element = array_arg[index];
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endfunction
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parameter integer IDX = 5;
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parameter integer CHK = 5;
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localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17};
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localparam element1 = array[IDX];
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localparam elementf = get_element(IDX, array);
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initial begin
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`checkh (element1, CHK);
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`checkh (elementf, CHK);
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end
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endmodule
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