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31 lines
663 B
Verilog
31 lines
663 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use.
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// SPDX-License-Identifier: CC0-1.0
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// bug541
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module t(clk,odata);
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input clk;
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output [7:0] odata;
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paramtest_DFFRE #(1) dffre0(clk,odata[7]);
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paramtest_WRAP #(7) dffe0(clk,odata[6:0]);
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endmodule
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module paramtest_WRAP(clk,q);
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parameter W=1;
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input clk;
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output [W-1:0] q;
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paramtest_DFFRE #(W) dffre0(clk,q);
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endmodule
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module paramtest_DFFRE(clk,q);
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parameter W=1;
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parameter [W-1:0] INIT={W{1'b0}};
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input clk;
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output [W-1:0] q;
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reg [W-1:0] q;
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always @(posedge clk) begin
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q <= INIT;
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end
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endmodule
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