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42 lines
636 B
Verilog
42 lines
636 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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package tt_pkg;
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typedef enum logic [1:0] {L0, L1, L2, L3} test_t;
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endpackage
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module t (/*AUTOARG*/
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// Outputs
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ob
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);
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output [1:0] ob;
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import tt_pkg::*;
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test_t a;
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test_t b;
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assign a = L0;
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assign ob = b;
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tt_buf #(.T_t(test_t))
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u_test
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(.i(a), .o(b));
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endmodule
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module tt_buf
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#(
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parameter type T_t = logic [0:0]
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)
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(
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input T_t i,
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output T_t o
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);
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assign o = i;
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endmodule
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