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35 lines
1009 B
Verilog
35 lines
1009 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Pierre-Henri Horrein
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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parameter DEPTH = 1;
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reg [DEPTH-1:0] shiftreg_gen;
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reg [DEPTH-1:0] shiftreg;
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reg my_sr_input = '1;
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// shiftreg_gen is generated: it should not raise any warning or error
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always_ff @(posedge clk) begin
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shiftreg_gen[0] <= my_sr_input;
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end
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if (DEPTH > 1) begin
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always_ff @(posedge clk) begin
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shiftreg_gen[DEPTH-1:1] <= shiftreg_gen[DEPTH-2:0];
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end
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end
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// shiftreg is not generated: it can raise a warning
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always_ff @(posedge clk) begin
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shiftreg[0] <= my_sr_input;
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/* verilator lint_off SELRANGE */
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if (DEPTH > 1) shiftreg[DEPTH-1:1] <= shiftreg[DEPTH-2:0];
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/* verilator lint_on SELRANGE */
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end
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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