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55 lines
1.3 KiB
Verilog
55 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Conor McCullough.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [63:0] from = 64'h0706050403020100;
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reg [7:0] to;
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reg [2:0] bitn;
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reg [7:0] cyc; initial cyc=0;
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always @* begin
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to = from[bitn * 8 +: 8];
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end
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always @ (posedge clk) begin
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cyc <= cyc + 8'd1;
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case (cyc)
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8'd00: begin bitn<=3'd0; end
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8'd01: begin bitn<=3'd1; end
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8'd02: begin bitn<=3'd2; end
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8'd03: begin bitn<=3'd3; end
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8'd04: begin bitn<=3'd4; end
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8'd05: begin bitn<=3'd5; end
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8'd06: begin bitn<=3'd6; end
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8'd07: begin bitn<=3'd7; end
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8'd08: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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default: ;
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endcase
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case (cyc)
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8'd00: ;
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8'd01: begin if (to !== 8'h00) $stop; end
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8'd02: begin if (to !== 8'h01) $stop; end
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8'd03: begin if (to !== 8'h02) $stop; end
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8'd04: begin if (to !== 8'h03) $stop; end
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8'd05: begin if (to !== 8'h04) $stop; end
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8'd06: begin if (to !== 8'h05) $stop; end
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8'd07: begin if (to !== 8'h06) $stop; end
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8'd08: begin if (to !== 8'h07) $stop; end
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default: $stop;
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endcase
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end
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endmodule
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