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119 lines
3.1 KiB
Verilog
119 lines
3.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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parameter DW = 4;
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wire [3:0] drv_a = crc[3:0];
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wire [3:0] drv_b = crc[7:4];
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wire [3:0] drv_e = crc[19:16];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [DW-1:0] drv; // To/From test1 of Test1.v
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wire [DW-1:0] drv2; // From test2 of Test2.v
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// End of automatics
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Test1 test1 (/*AUTOINST*/
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// Inouts
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.drv (drv[DW-1:0]),
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// Inputs
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.drv_a (drv_a[DW-1:0]),
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.drv_b (drv_b[DW-1:0]),
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.drv_e (drv_e[DW-1:0]));
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Test2 test2 (/*AUTOINST*/
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// Outputs
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.drv2 (drv2[DW-1:0]),
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// Inputs
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.drv_a (drv_a[DW-1:0]),
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.drv_b (drv_b[DW-1:0]),
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.drv_e (drv_e[DW-1:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, drv};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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if (drv2 != drv) $stop;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hd95d216c5a2945d0
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test1 #(
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parameter DW = 4
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)(
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input wire [DW-1:0] drv_a,
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input wire [DW-1:0] drv_b,
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input wire [DW-1:0] drv_e,
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inout wire [DW-1:0] drv
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);
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wire drv_0, drv_1, drv_2, drv_3;
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bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]);
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bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]);
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bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]);
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bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
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bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
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bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
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bufif1
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bufa3 (drv_3, drv_a[3], drv_e[3]),
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bufb3 (drv_3, drv_b[3], ~drv_e[3]);
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assign drv = {drv_3,drv_2,drv_1,drv_0};
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endmodule
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module Test2 #(
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parameter DW = 4
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)(
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input wire [DW-1:0] drv_a,
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input wire [DW-1:0] drv_b,
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input wire [DW-1:0] drv_e,
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inout wire [DW-1:0] drv2
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);
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wire [DW-1:0] drv_all;
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bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e);
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// Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e);
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bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]},
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{drv_b[3], drv_b[2], drv_b[1], drv_b[0]},
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{~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]});
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assign drv2 = drv_all;
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endmodule
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