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113 lines
2.3 KiB
Verilog
113 lines
2.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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integer a, b, c, d, e, f, g, h, i, j, k, l;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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//====================
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// Positive test cases
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//====================
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// Single if, which is untrue sometimes
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unique0 if (cyc > 5)
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a <= 17;
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// single if with else
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unique0 if (cyc < 3)
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b <= 17;
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else
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b <= 19;
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// multi if, some cases may not be true
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unique0 if (cyc < 3)
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c <= 17;
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else if (cyc > 3)
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c <= 19;
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// multi if with else, else clause hit in some cases
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unique0 if (cyc < 3)
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d <= 17;
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else if (cyc > 3)
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d <= 19;
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else
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d <= 21;
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// single if with else
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unique if (cyc < 3)
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f <= 17;
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else
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f <= 19;
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// multi if
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unique if (cyc < 3)
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g <= 17;
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else if (cyc >= 3)
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g <= 19;
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// multi if with else, else clause hit in some cases
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unique if (cyc < 3)
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h <= 17;
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else if (cyc > 3)
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h <= 19;
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else
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h <= 21;
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//====================
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// Negative test cases
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//====================
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`ifdef FAILING_ASSERTION1
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$display("testing fail 1: %d", cyc);
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// multi if, multiple cases true
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unique0 if (cyc < 3)
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i <= 17;
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else if (cyc < 5)
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i <= 19;
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`endif
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`ifdef FAILING_ASSERTION2
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// multi if, multiple cases true
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unique if (cyc < 3)
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j <= 17;
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else if (cyc < 5)
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j <= 19;
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`endif
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`ifdef FAILING_ASSERTION3
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// multi if, no cases true
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unique if (cyc > 1000)
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k <= 17;
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else if (cyc > 2000)
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k <= 19;
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`endif
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`ifdef FAILING_ASSERTION4
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// Single if, which is untrue sometimes.
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// The LRM states: "A software tool shall also issue an error if it determines that no condition'
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// is true, or it is possible that no condition is true, and the final if does not have a
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// corresponding else." In this case, the final if is the only if, but I think the clause
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// still applies.
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unique if (cyc > 5)
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l <= 17;
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`endif
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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