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49 lines
1.0 KiB
Verilog
49 lines
1.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`begin_keywords "VAMS-2.3"
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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task check (integer line, real got, real expec);
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real delta;
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delta = got-expec;
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if (delta > 0.001) begin
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$display("Line%d: Got %g Exp %g\n", line, got, expec);
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$stop;
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end
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endtask
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wreal wr;
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assign wr = 1.1;
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sub sub (.*);
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initial begin
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check(`__LINE__, sqrt(2.0) , 1.414);
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check(`__LINE__, pow(2.0,2.0) , 4.0);
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check(`__LINE__, ln(2.0) , 0.693147);
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check(`__LINE__, log(2.0) , 0.30103);
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check(`__LINE__, floor(2.5) , 2.0);
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check(`__LINE__, exp(2.0) , 7.38906);
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check(`__LINE__, ceil(2.5) , 3.0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (
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input wreal wr
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);
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initial begin
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if (wr != 1.1) $stop;
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end
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endmodule
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