67 lines
2.0 KiB
Verilog
67 lines
2.0 KiB
Verilog
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module hvsync(
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clk, hsync, vsync, inDisplayArea, CounterX, CounterY, pixel);
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input clk;
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output hsync, vsync;
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output inDisplayArea;
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output [8:0] CounterX;
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output [8:0] CounterY;
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output pixel;
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// constant declarations for VGA sync parameters
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localparam H_DISPLAY = 256; // horizontal display area
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localparam H_L_BORDER = 12; // horizontal left border
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localparam H_R_BORDER = 8; // horizontal right border
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localparam H_RETRACE = 24; // horizontal retrace
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localparam H_MAX = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
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localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
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localparam END_H_RETRACE = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
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localparam V_DISPLAY = 240; // vertical display area
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localparam V_T_BORDER = 4; // vertical top border
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localparam V_B_BORDER = 16; // vertical bottom border
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localparam V_RETRACE = 2; // vertical retrace
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localparam V_MAX = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
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localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
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localparam END_V_RETRACE = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
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reg [8:0] CounterX;
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reg [8:0] CounterY;
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reg pixel;
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wire CounterXmaxed = (CounterX==H_MAX);
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wire CounterYmaxed = (CounterY==V_MAX);
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always @(posedge clk)
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if(CounterXmaxed)
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CounterX <= 0;
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else
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CounterX <= CounterX + 1;
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always @(posedge clk)
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if(CounterXmaxed)
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if (!CounterYmaxed)
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CounterY <= CounterY + 1;
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else
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CounterY <= 0;
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reg vga_HS, vga_VS;
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always @(posedge clk)
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begin
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vga_HS <= (CounterX>=280 && CounterX<288); // change this value to move the display horizontally
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vga_VS <= (CounterY==START_V_RETRACE); // change this value to move the display vertically
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end
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reg inDisplayArea;
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always @(posedge clk)
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begin
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inDisplayArea <= (CounterX<H_DISPLAY) && (CounterY<V_DISPLAY);
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pixel <= inDisplayArea &&
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(((CounterX&7)==0) || ((CounterY&7)==0));
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end
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assign hsync = ~vga_HS;
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assign vsync = ~vga_VS;
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endmodule
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