mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-27 01:51:35 +00:00
20 lines
361 B
Verilog
20 lines
361 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2007 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t (/*AUTOARG*/
|
|
// Inputs
|
|
clk
|
|
);
|
|
|
|
input clk;
|
|
|
|
always @ (posedge clk) begin
|
|
assert (0);
|
|
$finish;
|
|
end
|
|
|
|
endmodule
|