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106 lines
2.7 KiB
Verilog
106 lines
2.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Peter Monsson.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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wire [31:0] in = cyc;
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Test test (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.in (in[31:0]));
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Test2 test2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.in (in[31:0]));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Inputs
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clk, in
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);
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input clk;
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input [31:0] in;
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reg [31:0] dly0 = 0;
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reg [31:0] dly1 = 1;
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reg [31:0] dly2 = -1;
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// If called in an assertion, sequence, or property, the appropriate clocking event.
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// Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit.
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// Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used.
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// Otherwise, if called in a procedure, the inferred clock
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// Otherwise, default clocking
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always @(posedge clk) begin
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dly0 <= in;
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dly1 <= in;
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dly2 <= in;
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// In clock expression
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$write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0));
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if ($rose(dly0[4])) $stop;
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if ($fell(dly1[4])) $stop;
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if ($stable(dly2)) $stop;
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if (!$changed(dly2)) $stop;
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end
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assert property (@(posedge clk) $rose(dly0) || dly0%2==0);
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assert property (@(posedge clk) $fell(dly1) || dly1%2==1);
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assert property (@(posedge clk) !$stable(dly2));
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assert property (@(posedge clk) $changed(dly2));
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endmodule
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module Test2 (/*AUTOARG*/
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// Inputs
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clk, in
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);
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input clk;
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input [31:0] in;
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reg [31:0] dly0;
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reg [31:0] dly1 = 1;
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reg [31:0] dly2;
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always @(posedge clk) begin
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dly0 <= in;
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dly1 <= in;
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dly2 <= in;
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if ($rose(dly0[31:4])) $stop;
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if ($fell(dly1[31:4])) $stop;
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if (!$stable(dly2[31:4])) $stop;
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if ($changed(dly2[31:4])) $stop;
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end
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default clocking @(posedge clk); endclocking
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assert property ($rose(dly0[0]) || dly0%2==0);
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default clocking @(posedge clk); endclocking
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assert property ($fell(dly1[0]) || dly1%2==1);
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default clocking @(posedge clk); endclocking
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assert property ($stable(dly2[31:4]));
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assert property (!$changed(dly2[31:4]));
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endmodule
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