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105 lines
2.7 KiB
Verilog
105 lines
2.7 KiB
Verilog
`include "hvsync_generator.v"
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`include "lfsr.v"
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module sound_generator(clk, reset, spkr,
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lfo_freq,noise_freq, vco_freq,
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vco_select, noise_select, lfo_shift, mixer);
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input clk, reset;
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output reg spkr = 0; // module output
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input [9:0] lfo_freq; // LFO frequency (10 bits)
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input [11:0] noise_freq; // noise frequency (12 bits)
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input [11:0] vco_freq; // VCO frequency (12 bits)
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input vco_select; // 1 = LFO modulates VCO
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input noise_select; // 1 = LFO modulates Noise
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input [2:0] lfo_shift; // LFO modulation depth
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input [2:0] mixer; // mix enable {LFO, Noise, VCO}
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reg [3:0] div16; // divide-by-16 counter
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reg [17:0] lfo_count; // LFO counter (18 bits)
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reg lfo_state; // LFO output
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reg [12:0] noise_count; // Noise counter (13 bits)
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reg noise_state; // Noise output
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reg [12:0] vco_count; // VCO counter (12 bits)
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reg vco_state; // VCO output
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reg [15:0] lfsr; // LFSR output
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LFSR #(16'b1000000001011,0) lfsr_gen(
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.clk(clk),
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.reset(reset),
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.enable(div16 == 0 && noise_count == 0),
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.lfsr(lfsr)
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);
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// create triangle waveform from LFO
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wire [11:0] lfo_triangle = lfo_count[17] ? ~lfo_count[17:6] : lfo_count[17:6];
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wire [11:0] vco_delta = lfo_triangle >> lfo_shift;
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always @(posedge clk) begin
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// divide clock by 64
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div16 <= div16 + 1;
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if (div16 == 0) begin
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// VCO oscillator
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if (reset || vco_count == 0) begin
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vco_state <= ~vco_state;
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if (vco_select)
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vco_count <= vco_freq + vco_delta;
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else
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vco_count <= vco_freq + 0;
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end else
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vco_count <= vco_count - 1;
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// LFO oscillator
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if (reset || lfo_count == 0) begin
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lfo_state <= ~lfo_state;
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lfo_count <= {lfo_freq, 8'b0};
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end else
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lfo_count <= lfo_count - 1;
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// Noise oscillator
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if (reset || noise_count == 0) begin
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if (lfsr[0])
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noise_state <= ~noise_state;
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if (noise_select)
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noise_count <= noise_freq + vco_delta;
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else
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noise_count <= noise_freq + 0;
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end else
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noise_count <= noise_count - 1;
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// Mixer
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spkr <= (lfo_state | ~mixer[2])
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& (noise_state | ~mixer[1])
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& (vco_state | ~mixer[0]);
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end
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end
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endmodule
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module test_snchip_top(clk, reset, hsync, vsync, rgb, spkr);
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input clk, reset;
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output hsync;
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output vsync;
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output spkr;
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output [2:0] rgb;
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// don't output a valid sync signal
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assign hsync = 0;
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assign vsync = 0;
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assign rgb = {spkr,1'b0,1'b0};
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sound_generator sndgen(
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.clk(clk),
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.reset(reset),
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.spkr(spkr),
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.lfo_freq(1000),
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.noise_freq(90),
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.vco_freq(250),
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.vco_select(1),
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.noise_select(1),
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.lfo_shift(1),
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.mixer(3)
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);
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endmodule
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