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https://github.com/sehugg/8bitworkshop.git
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202 lines
4.6 KiB
Verilog
202 lines
4.6 KiB
Verilog
`ifndef DIGITS10_H
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`define DIGITS10_H
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`include "hvsync_generator.v"
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// module for 10-digit bitmap ROM
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module digits10_case(digit, yofs, bits);
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input [3:0] digit; // digit 0-9
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input [2:0] yofs; // vertical offset (0-4)
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output reg [4:0] bits; // output (5 bits)
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// combine {digit,yofs} into single ROM address
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wire [6:0] caseexpr = {digit,yofs};
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always @(*)
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case (caseexpr)/*{w:5,h:5,count:10}*/
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7'o00: bits = 5'b11111;
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7'o01: bits = 5'b10001;
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7'o02: bits = 5'b10001;
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7'o03: bits = 5'b10001;
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7'o04: bits = 5'b11111;
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7'o10: bits = 5'b01100;
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7'o11: bits = 5'b00100;
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7'o12: bits = 5'b00100;
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7'o13: bits = 5'b00100;
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7'o14: bits = 5'b11111;
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7'o20: bits = 5'b11111;
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7'o21: bits = 5'b00001;
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7'o22: bits = 5'b11111;
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7'o23: bits = 5'b10000;
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7'o24: bits = 5'b11111;
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7'o30: bits = 5'b11111;
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7'o31: bits = 5'b00001;
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7'o32: bits = 5'b11111;
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7'o33: bits = 5'b00001;
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7'o34: bits = 5'b11111;
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7'o40: bits = 5'b10001;
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7'o41: bits = 5'b10001;
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7'o42: bits = 5'b11111;
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7'o43: bits = 5'b00001;
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7'o44: bits = 5'b00001;
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7'o50: bits = 5'b11111;
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7'o51: bits = 5'b10000;
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7'o52: bits = 5'b11111;
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7'o53: bits = 5'b00001;
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7'o54: bits = 5'b11111;
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7'o60: bits = 5'b11111;
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7'o61: bits = 5'b10000;
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7'o62: bits = 5'b11111;
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7'o63: bits = 5'b10001;
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7'o64: bits = 5'b11111;
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7'o70: bits = 5'b11111;
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7'o71: bits = 5'b00001;
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7'o72: bits = 5'b00001;
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7'o73: bits = 5'b00001;
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7'o74: bits = 5'b00001;
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7'o100: bits = 5'b11111;
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7'o101: bits = 5'b10001;
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7'o102: bits = 5'b11111;
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7'o103: bits = 5'b10001;
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7'o104: bits = 5'b11111;
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7'o110: bits = 5'b11111;
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7'o111: bits = 5'b10001;
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7'o112: bits = 5'b11111;
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7'o113: bits = 5'b00001;
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7'o114: bits = 5'b11111;
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default: bits = 0;
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endcase
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endmodule
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module digits10_array(digit, yofs, bits);
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input [3:0] digit; // digit 0-9
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input [2:0] yofs; // vertical offset (0-4)
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output [4:0] bits; // output (5 bits)
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reg [4:0] bitarray[0:15][0:4]; // ROM array
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assign bits = bitarray[digit][yofs]; // assign module output
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integer i,j;
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initial begin/*{w:5,h:5,count:10}*/
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bitarray[0][0] = 5'b11111;
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bitarray[0][1] = 5'b10001;
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bitarray[0][2] = 5'b10001;
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bitarray[0][3] = 5'b10001;
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bitarray[0][4] = 5'b11111;
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bitarray[1][0] = 5'b01100;
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bitarray[1][1] = 5'b00100;
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bitarray[1][2] = 5'b00100;
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bitarray[1][3] = 5'b00100;
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bitarray[1][4] = 5'b11111;
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bitarray[2][0] = 5'b11111;
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bitarray[2][1] = 5'b00001;
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bitarray[2][2] = 5'b11111;
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bitarray[2][3] = 5'b10000;
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bitarray[2][4] = 5'b11111;
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bitarray[3][0] = 5'b11111;
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bitarray[3][1] = 5'b00001;
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bitarray[3][2] = 5'b11111;
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bitarray[3][3] = 5'b00001;
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bitarray[3][4] = 5'b11111;
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bitarray[4][0] = 5'b10001;
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bitarray[4][1] = 5'b10001;
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bitarray[4][2] = 5'b11111;
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bitarray[4][3] = 5'b00001;
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bitarray[4][4] = 5'b00001;
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bitarray[5][0] = 5'b11111;
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bitarray[5][1] = 5'b10000;
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bitarray[5][2] = 5'b11111;
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bitarray[5][3] = 5'b00001;
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bitarray[5][4] = 5'b11111;
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bitarray[6][0] = 5'b11111;
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bitarray[6][1] = 5'b10000;
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bitarray[6][2] = 5'b11111;
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bitarray[6][3] = 5'b10001;
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bitarray[6][4] = 5'b11111;
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bitarray[7][0] = 5'b11111;
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bitarray[7][1] = 5'b00001;
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bitarray[7][2] = 5'b00001;
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bitarray[7][3] = 5'b00001;
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bitarray[7][4] = 5'b00001;
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bitarray[8][0] = 5'b11111;
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bitarray[8][1] = 5'b10001;
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bitarray[8][2] = 5'b11111;
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bitarray[8][3] = 5'b10001;
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bitarray[8][4] = 5'b11111;
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bitarray[9][0] = 5'b11111;
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bitarray[9][1] = 5'b10001;
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bitarray[9][2] = 5'b11111;
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bitarray[9][3] = 5'b00001;
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bitarray[9][4] = 5'b11111;
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// clear unused array entries
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for (i = 10; i <= 15; i++)
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for (j = 0; j <= 4; j++)
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bitarray[i][j] = 0;
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end
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endmodule
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// test module
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module test_numbers_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [3:0] digit = hpos[7:4];
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wire [2:0] xofs = hpos[3:1];
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wire [2:0] yofs = vpos[3:1];
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wire [4:0] bits;
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digits10_array numbers(
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.digit(digit),
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.yofs(yofs),
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.bits(bits)
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);
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wire r = display_on && 0;
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wire g = display_on && bits[xofs ^ 3'b111];
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wire b = display_on && 0;
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assign rgb = {b,g,r};
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endmodule
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`endif
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