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40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
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`include "hvsync_generator.v"
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/*
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A simple test pattern using the hvsync_generator module.
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*/
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module test_hvsync_top(clk, reset, hsync, vsync, rgb);
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input clk, reset; // clock and reset signals (input)
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output hsync, vsync; // H/V sync signals (output)
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output [2:0] rgb; // RGB output (BGR order)
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wire display_on; // display_on signal
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wire [8:0] hpos; // 9-bit horizontal position
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wire [8:0] vpos; // 9-bit vertical position
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// Include the H-V Sync Generator module and
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// wire it to inputs, outputs, and wires.
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(0),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// Assign each color bit to individual wires.
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wire r = display_on && (((hpos&7)==0) || ((vpos&7)==0));
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wire g = display_on && vpos[4];
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wire b = display_on && hpos[4];
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// Concatenation operator merges the red, green, and blue signals
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// into a single 3-bit vector, which is assigned to the 'rgb'
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// output. The IDE expects this value in BGR order.
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assign rgb = {b,g,r};
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endmodule
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