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53 lines
979 B
Verilog
53 lines
979 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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module top (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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tri pad_io_h;
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tri pad_io_l;
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sub sub (.*);
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endmodule
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module sub (/*AUTOARG*/
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// Inouts
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pad_io_h, pad_io_l
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);
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parameter USE = 1'b1;
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parameter DIFFERENTIAL = 1'b1;
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parameter BIDIR = 1'b1;
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inout pad_io_h;
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inout pad_io_l;
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wire [31:0] dqs_out_dtap_delay;
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generate
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if (USE) begin: output_strobe
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wire aligned_os_oe;
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wire aligned_strobe;
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if (BIDIR) begin
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reg sig_h_r = 1'b0;
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reg sig_l_r = 1'b0;
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always @* begin
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sig_h_r = ~aligned_os_oe ? aligned_strobe : 1'bz;
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if (DIFFERENTIAL)
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sig_l_r = ~aligned_os_oe ? ~aligned_strobe : 1'bz;
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end
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assign pad_io_h = sig_h_r;
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if (DIFFERENTIAL)
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assign pad_io_l = sig_l_r;
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end
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end
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endgenerate
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endmodule
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