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244 lines
6.1 KiB
Verilog
244 lines
6.1 KiB
Verilog
`include "hvsync_generator.v"
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`include "ram.v"
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module example_bitmap_rom(addr, data);
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input [15:0] addr;
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output [15:0] data;
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reg [15:0] bitarray[0:255];
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assign data = bitarray[addr & 15];
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initial begin/*{w:16,h:16,bpw:16,count:1}*/
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bitarray[8'h00] = 16'b11110000000;
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bitarray[8'h01] = 16'b100001000000;
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bitarray[8'h02] = 16'b1111111100000;
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bitarray[8'h03] = 16'b1111111100000;
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bitarray[8'h04] = 16'b11110000000;
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bitarray[8'h05] = 16'b11111111110000;
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bitarray[8'h06] = 16'b111100001111000;
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bitarray[8'h07] = 16'b1111101101111100;
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bitarray[8'h08] = 16'b1101100001101111;
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bitarray[8'h09] = 16'b1101111111100110;
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bitarray[8'h0a] = 16'b1001111111100000;
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bitarray[8'h0b] = 16'b1111111100000;
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bitarray[8'h0c] = 16'b1110011100000;
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bitarray[8'h0d] = 16'b1100001100000;
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bitarray[8'h0e] = 16'b1100001100000;
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bitarray[8'h0f] = 16'b11100001110000;
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end
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endmodule
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module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
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ram_addr, ram_data, ram_busy,
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rom_addr, rom_data);
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parameter NB = 5;
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parameter MB = 3;
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localparam N = 1<<NB;
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localparam M = 1<<MB;
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input clk, reset;
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input [8:0] hpos;
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input [8:0] vpos;
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output [3:0] rgb;
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output [NB:0] ram_addr;
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input [15:0] ram_data;
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output ram_busy;
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output [15:0] rom_addr;
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input [15:0] rom_data;
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reg [7:0] sprite_xpos[0:N-1];
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reg [7:0] sprite_ypos[0:N-1];
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reg [7:0] sprite_attr[0:N-1];
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reg [NB-1:0] sprite_to_line[0:M-1];
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reg [7:0] line_xpos[0:M-1];
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reg [7:0] line_yofs[0:M-1];
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reg [7:0] line_attr[0:M-1];
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reg line_active[0:M-1];
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reg [3:0] scanline[0:511];
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reg [NB-1:0] i; // 0..N-1
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reg [MB-1:0] j; // 0..M-1
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reg [MB-1:0] k; // 0..M-1
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reg [7:0] z;
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reg [8:0] write_ofs;
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wire [8:0] read_bufidx = {vpos[0], hpos[7:0]};
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reg [15:0] out_bitmap;
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reg [7:0] out_attr;
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wire [NB-1:0] load_index = hpos[NB+2:3];
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/*
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0: read sprite_ypos[i]
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1: check ypos, write line_ypos[j]
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...
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0: read line_xpos[0]
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1: store xpos
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2: read line_ypos[0]
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3: store ypos
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4: read line_attr[0]
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5: store attr
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8: write 16 pixels
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*/
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always @(posedge clk) begin
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ram_busy <= 0;
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// reset every frame, don't draw vpos >= 256
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if (reset || vpos[8]) begin
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// load sprites from RAM on line 260
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// 8 cycles per sprite
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// do first sprite twice b/c CPU might still be busy
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if (vpos == 260 && hpos < N*8+8) begin
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ram_busy <= 1;
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case (hpos[2:0])
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3: begin
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ram_addr <= {load_index, 1'b0};
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end
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5: begin
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sprite_xpos[load_index] <= ram_data[7:0];
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sprite_ypos[load_index] <= ram_data[15:8];
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ram_addr <= {load_index, 1'b1};
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end
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7: begin
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sprite_attr[load_index] <= ram_data[7:0];
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end
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endcase
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end
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end else if (hpos < N*2) begin
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k <= 0;
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// select the sprites that will appear in this scanline
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case (hpos[0])
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// compute Y offset of sprite relative to scanline
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0: z <= 8'(vpos - sprite_ypos[i]);
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// sprite is active if Y offset is 0..15
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1: begin
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if (z < 16) begin
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line_yofs[j] <= z; // save Y offset
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sprite_to_line[j] <= i; // save main array index
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line_active[j] <= 1; // mark sprite active
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j <= j + 1; // inc counter
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end
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i <= i + 1; // inc main array counter
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end
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endcase
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end else if (hpos < N*2+M*24) begin
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j <= 0;
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// divide hpos by 24 (8 setup + 16 render)
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if ((hpos[3:0] < 8) ^^ hpos[4]) begin
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// render sprites into write buffer
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case (hpos[3:0])
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// grab index into main sprite array
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0: i <= sprite_to_line[k];
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// load scanline buffer offset to write
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1: write_ofs <= {~vpos[0], sprite_xpos[i]};
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// set ROM address and fetch bitmap
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2: rom_addr <= {4'b0, sprite_attr[i][7:4], line_yofs[k]};
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// fetch 0 if sprite is inactive
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3: out_bitmap <= line_active[k] ? rom_data : 0;
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// load attribute for sprite
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4: out_attr <= sprite_attr[i];
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// disable sprite for next scanline
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6: line_active[k] <= 0;
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// go to next sprite in 2ndary buffer
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7: k <= k + 1;
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endcase
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end else begin
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// write color to scanline buffer if low bit == 1
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if (out_bitmap[0])
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scanline[write_ofs] <= out_attr[3:0];
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// shift bits right
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out_bitmap <= out_bitmap >> 1;
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// increment to next scanline pixel
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write_ofs <= write_ofs + 1;
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end
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end else begin
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// clear counters
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i <= 0;
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end
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// read and clear buffer
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rgb <= scanline[read_bufidx];
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scanline[read_bufidx] <= 0;
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end
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endmodule
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module test_scanline_render_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [3:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [15:0] rom_addr;
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wire [15:0] rom_data;
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example_bitmap_rom bitmap_rom(
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.addr(rom_addr),
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.data(rom_data)
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);
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wire [5:0] ram_addr;
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wire [15:0] ram_read;
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reg [15:0] ram_write;
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reg ram_we;
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wire ram_busy;
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// 64-word RAM
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RAM_sync #(6,16) ram(
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.clk(clk),
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.addr(ram_addr),
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.dout(ram_read),
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.din(ram_write),
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.we(ram_we)
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);
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sprite_scanline_renderer ssr(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.rgb(rgb),
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.ram_addr(ram_addr),
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.ram_data(ram_read),
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.ram_busy(ram_busy),
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.rom_addr(rom_addr),
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.rom_data(rom_data)
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);
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always @(posedge clk) begin
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// wiggle sprites randomly once per frame
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if (vpos == 256) begin
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ram_addr <= hpos[7:2];
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// 4 clocks per read/write cycle
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if (!hpos[1]) begin
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ram_we <= 0;
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end else begin
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ram_we <= 1;
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ram_write <= ram_read + 16'(($random&3)-1);
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end
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end else
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ram_we <= 0;
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end
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endmodule
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