mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-29 14:51:17 +00:00
38 lines
891 B
Verilog
38 lines
891 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2020 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module foo
|
|
#( parameter real bar = 2.0)
|
|
();
|
|
|
|
endmodule
|
|
|
|
module t();
|
|
|
|
genvar m, r;
|
|
generate
|
|
for (m = 10; m <= 20; m+=10) begin : gen_m
|
|
for (r = 0; r <= 1; r++) begin : gen_r
|
|
localparam real lparam = m + (r + 0.5);
|
|
initial begin
|
|
if (lparam != foo_inst.bar) begin
|
|
$display("%m: lparam != foo_inst.bar (%f, %f)",
|
|
lparam, foo_inst.bar);
|
|
$stop();
|
|
end
|
|
end
|
|
|
|
foo #(.bar (lparam)) foo_inst ();
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
initial begin
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
|
|
endmodule
|