64 lines
1.8 KiB
Verilog
64 lines
1.8 KiB
Verilog
`ifndef HVSYNC_GENERATOR_H
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`define HVSYNC_GENERATOR_H
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module hvsync_generator(
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clk, hsync, vsync, display_on, hpos, vpos);
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input clk;
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output hsync, vsync;
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output reg display_on;
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output reg [8:0] hpos;
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output reg [8:0] vpos;
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// constant declarations for VGA sync parameters
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localparam H_DISPLAY = 256; // horizontal display area
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localparam H_L_BORDER = 16; // horizontal left border
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localparam H_R_BORDER = 16; // horizontal right border
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localparam H_RETRACE = 16; // horizontal retrace
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localparam H_MAX = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
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localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
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localparam END_H_RETRACE = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
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localparam V_DISPLAY = 240; // vertical display area
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localparam V_T_BORDER = 4; // vertical top border
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localparam V_B_BORDER = 14; // vertical bottom border
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localparam V_RETRACE = 4; // vertical retrace
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localparam V_MAX = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
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localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
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localparam END_V_RETRACE = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
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wire hmaxxed = (hpos==H_MAX);
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wire vmaxxed = (vpos==V_MAX);
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always @(posedge clk)
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if(hmaxxed)
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hpos <= 0;
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else
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hpos <= hpos + 1;
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always @(posedge clk)
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if(hmaxxed)
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if (!vmaxxed)
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vpos <= vpos + 1;
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else
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vpos <= 0;
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reg vga_HS, vga_VS;
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always @(posedge clk)
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begin
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vga_HS <= (hpos>=START_H_RETRACE && hpos<=END_H_RETRACE);
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vga_VS <= (vpos==START_V_RETRACE);
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end
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always @(posedge clk)
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begin
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display_on <= (hpos<H_DISPLAY) && (vpos<V_DISPLAY);
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end
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assign hsync = ~vga_HS;
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assign vsync = ~vga_VS;
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endmodule
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`endif
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