27 lines
611 B
Verilog
27 lines
611 B
Verilog
`ifndef LFSR_V
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`define LFSR_V
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module LFSR(clk, reset, enable, lfsr);
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parameter TAPS = 8'b11101; // bitmask for taps
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parameter INVERT = 0; // invert feedback bit?
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localparam NBITS = $size(TAPS); // bit width (derived from TAPS)
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input clk, reset;
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input enable; // only perform shift when enable=1
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output reg [NBITS-1:0] lfsr; // shift register
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wire feedback = lfsr[NBITS-1] ^ INVERT;
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always @(posedge clk)
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begin
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if (reset)
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lfsr <= {lfsr[NBITS-2:0], ~lfsr[0]};
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else if (enable)
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lfsr <= {lfsr[NBITS-2:0], 1'b0} ^ (feedback ? TAPS : 0);
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end
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endmodule
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`endif
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