mirror of
https://github.com/sehugg/8bitworkshop.git
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341 lines
9.0 KiB
Verilog
341 lines
9.0 KiB
Verilog
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`ifndef CPU16_H
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`define CPU16_H
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// ALU operations
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`define OP_ZERO 4'h0
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`define OP_LOAD_A 4'h1
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`define OP_INC 4'h2
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`define OP_DEC 4'h3
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`define OP_ASL 4'h4
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`define OP_LSR 4'h5
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`define OP_ROL 4'h6
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`define OP_ROR 4'h7
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`define OP_OR 4'h8
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`define OP_AND 4'h9
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`define OP_XOR 4'ha
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`define OP_LOAD_B 4'hb
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`define OP_ADD 4'hc
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`define OP_SUB 4'hd
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`define OP_ADC 4'he
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`define OP_SBB 4'hf
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module ALU(A, B, carry, aluop, Y);
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parameter N = 8; // default width = 8 bits
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input [N-1:0] A; // A input
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input [N-1:0] B; // B input
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input carry; // carry input
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input [3:0] aluop; // alu operation
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output [N:0] Y; // Y output + carry
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always @(*)
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case (aluop)
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// unary operations
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`OP_ZERO: Y = 0;
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`OP_LOAD_A: Y = {1'b0, A};
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`OP_INC: Y = A + 1;
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`OP_DEC: Y = A - 1;
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// unary operations that generate and/or use carry
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`OP_ASL: Y = {A, 1'b0};
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`OP_LSR: Y = {A[0], 1'b0, A[N-1:1]};
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`OP_ROL: Y = {A, carry};
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`OP_ROR: Y = {A[0], carry, A[N-1:1]};
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// binary operations
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`OP_OR: Y = {1'b0, A | B};
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`OP_AND: Y = {1'b0, A & B};
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`OP_XOR: Y = {1'b0, A ^ B};
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`OP_LOAD_B: Y = {1'b0, B};
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// binary operations that generate and/or use carry
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`OP_ADD: Y = A + B;
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`OP_SUB: Y = A - B;
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`OP_ADC: Y = A + B + (carry?1:0);
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`OP_SBB: Y = A - B - (carry?1:0);
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endcase
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endmodule
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/*
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00000aaa 0++++bbb operation A+B->A
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00001aaa 0++++bbb operation A+[B]->A
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00011aaa 0++++000 operation A+imm16 -> A
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00101aaa ######## load zero page
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00110aaa ######## store zero page
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01001aaa #####bbb load [B+#] -> A
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01010aaa #####bbb store A -> [B+#]
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01101aaa 0++++000 operation A+[imm16] -> A
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01110aaa 00cccbbb store A -> [B+#], C -> IP
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1000tttt ######## conditional branch
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11+++aaa ######## immediate binary operation
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*/
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module CPU16(clk, reset, hold, busy,
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address, data_in, data_out, write);
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input clk;
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input reset;
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input hold;
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output busy;
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output [15:0] address;
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input [15:0] data_in;
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output [15:0] data_out;
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output write;
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// wait state for RAM?
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parameter RAM_WAIT = 1;
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reg [15:0] regs[0:7]; // 8 16-bit registers
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reg [2:0] state; // CPU state
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reg carry; // carry flag
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reg zero; // zero flag
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reg neg; // negative flag
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wire [16:0] Y; // ALU 16-bit + carry output
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reg [3:0] aluop; // ALU operation
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reg [15:0] opcode; // used to decode ALU inputs
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wire [2:0] rdest = opcode[10:8]; // ALU A input reg.
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wire [2:0] rsrc = opcode[2:0]; // ALU B input reg.
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wire Bconst = opcode[15]; // ALU B = 8-bit constant
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wire Bload = opcode[11]; // ALU B = data bus
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// CPU states
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localparam S_RESET = 0;
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localparam S_SELECT = 1;
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localparam S_DECODE = 2;
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localparam S_COMPUTE = 3;
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localparam S_DECODE_WAIT = 4;
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localparam S_COMPUTE_WAIT = 5;
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localparam SP = 6; // stack ptr = register 6
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localparam IP = 7; // IP = register 7
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ALU #(16) alu(
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.A(regs[rdest]),
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.B(Bconst ? {8'b0, opcode[7:0]}
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: Bload ? data_in
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: regs[rsrc]),
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.Y(Y),
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.aluop(aluop),
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.carry(carry));
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always @(posedge clk)
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if (reset) begin
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state <= S_RESET;
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busy <= 1;
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end else begin
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case (state)
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// state 0: reset
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S_RESET: begin
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regs[IP] <= 16'h8000;
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write <= 0;
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state <= S_SELECT;
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end
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// state 1: select opcode address
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S_SELECT: begin
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write <= 0;
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if (hold) begin
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busy <= 1;
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state <= S_SELECT;
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end else begin
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busy <= 0;
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address <= regs[IP];
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regs[IP] <= regs[IP] + 1;
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state <= RAM_WAIT ? S_DECODE_WAIT : S_DECODE;
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end
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end
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// state 2: read/decode opcode
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S_DECODE: begin
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// default next state
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state <= RAM_WAIT && data_in[11] ? S_COMPUTE_WAIT : S_COMPUTE;
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casez (data_in)
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// 00000aaa0++++bbb operation A+B->A
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16'b00000???0???????: begin
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aluop <= data_in[6:3];
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end
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// 00001aaa01+++bbb operation A+[B]->A
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16'b00001???01??????: begin
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address <= regs[data_in[2:0]];
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aluop <= data_in[6:3];
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if (data_in[2:0] == SP)
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regs[SP] <= regs[SP] + 1;
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end
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// 00011aaa0++++000 operation A+imm16 -> A
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16'b00011???0????000: begin
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address <= regs[IP];
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regs[IP] <= regs[IP] + 1;
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aluop <= data_in[6:3];
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end
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// 11+++aaa######## immediate binary operation
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16'b11??????????????: begin
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aluop <= data_in[14:11];
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end
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// 00101aaa######## load ZP memory
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16'b00101???????????: begin
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address <= {8'b0, data_in[7:0]};
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aluop <= `OP_LOAD_B;
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end
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// 00110aaa######## store ZP memory
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16'b00110???????????: begin
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address <= {8'b0, data_in[7:0]};
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data_out <= regs[data_in[10:8]];
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write <= 1;
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state <= S_SELECT;
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end
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// 01001aaa#####bbb [B+#] -> A
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16'b01001???????????: begin
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address <= regs[data_in[2:0]] + 16'($signed(data_in[7:3]));
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aluop <= `OP_LOAD_B;
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if (data_in[2:0] == SP)
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regs[SP] <= regs[SP] + 1;
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end
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// 01010aaa#####bbb store A -> [B+#]
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16'b01010???????????: begin
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address <= regs[data_in[2:0]] + 16'($signed(data_in[7:3]));
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data_out <= regs[data_in[10:8]];
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write <= 1;
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state <= S_SELECT;
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if (data_in[2:0] == SP)
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regs[SP] <= regs[SP] - 1;
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end
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// 01011aaa0++++000 operation A+[imm16] -> A
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16'b01011????????000: begin
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address <= regs[IP];
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regs[IP] <= regs[IP] + 1;
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aluop <= data_in[6:3];
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end
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// 01110aaa00cccbbb store A -> [B], C -> IP
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16'b01110???00??????: begin
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address <= regs[data_in[2:0]];
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data_out <= regs[data_in[10:8]];
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write <= 1;
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state <= S_SELECT;
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if (data_in[2:0] == SP)
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regs[SP] <= regs[SP] - 1;
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regs[IP] <= regs[data_in[5:3]];
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end
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// 1000????######## conditional branch
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16'b1000????????????: begin
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if (
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(data_in[8] && (data_in[11] == carry)) ||
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(data_in[9] && (data_in[11] == zero)) ||
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(data_in[10] && (data_in[11] == neg)))
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begin
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// relative branch, sign extended
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regs[IP] <= regs[IP] + 16'($signed(data_in[7:0]));
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end
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state <= S_SELECT;
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end
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// fall-through RESET
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default: begin
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state <= S_RESET; // reset
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end
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endcase
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opcode <= data_in; // (only use opcode next cycle)
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end
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// state 3: compute ALU op and flags
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S_COMPUTE: begin
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// transfer ALU output to destination
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regs[rdest] <= Y[15:0];
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// set carry for certain operations (4-7,12-15)
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if (aluop[2]) carry <= Y[16];
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// set zero flag
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zero <= ~|Y[15:0];
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neg <= Y[15];
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// repeat CPU loop
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state <= S_SELECT;
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end
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// wait 1 cycle for RAM read
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S_DECODE_WAIT: begin
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state <= S_DECODE;
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end
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S_COMPUTE_WAIT : begin
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state <= S_COMPUTE;
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end
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endcase
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end
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endmodule
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`ifdef TOPMOD__test_CPU16_top
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module test_CPU16_top(
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input clk,
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input reset,
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output [15:0] address_bus,
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output reg [15:0] to_cpu,
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output [15:0] from_cpu,
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output write_enable,
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output [15:0] IP,
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output zero,
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output carry,
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output busy,
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output [2:0] state
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);
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reg [15:0] ram[0:65535];
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reg [15:0] rom[0:255];
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assign IP = cpu.regs[7];
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assign zero = cpu.zero;
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assign carry = cpu.carry;
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assign state = cpu.state;
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CPU16 cpu(
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.clk(clk),
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.reset(reset),
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.hold(0),
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.busy(busy),
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.address(address_bus),
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.data_in(to_cpu),
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.data_out(from_cpu),
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.write(write_enable));
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always @(posedge clk)
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if (write_enable) begin
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ram[address_bus] <= from_cpu;
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end
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always @(posedge clk)
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if (address_bus[15] == 0)
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to_cpu <= ram[address_bus];
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else
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to_cpu <= rom[address_bus[7:0]];
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`ifdef EXT_INLINE_ASM
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initial begin
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rom = '{
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__asm
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.arch femto16
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.org 0x8000
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.len 256
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mov sp,@$6fff
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mov dx,@Fib
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jsr dx
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reset
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Fib:
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mov ax,#1
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mov bx,#0
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Loop:
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mov cx,ax
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add ax,bx
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mov bx,cx
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push ax
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pop ax
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mov [42],ax
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mov ax,[42]
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bcc Loop
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rts
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__endasm
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};
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end
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`endif
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endmodule
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`endif
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`endif
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