Steven Hugg 42920337ec verilog: fix optimization for tick2(), removed > 64 bit tests, stop tracing when $stop/$finish, +SignExt		2021-07-08 15:50:16 -05:00
..
darksocv.v
t_alw_combdly.v
t_alw_dly.v
t_alw_nosplit.v
t_alw_reorder.v
t_alw_split_rst.v
t_alw_split.v
t_alw_splitord.v
t_array_compare.v
t_assert_basic.v
t_assert_casez.v
t_assert_comp.v
t_assert_cover.v
t_assert_disable_iff.v
t_assert_elab.v
t_assert_implication.v
t_assert_on.v
t_assert_property.v
t_assert_question.v
t_assert_synth.v	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
t_assign_inline.v
t_attr_parenstar.v
t_bitsel_enum.v
t_bitsel_slice.v
t_blocking.v
t_case_deep.v
t_case_dupitems.v
t_case_group.v
t_case_huge_sub3.v
t_case_itemwidth.v
t_case_onehot.v
t_case_orig.v
t_case_reducer.v
t_case_x.v
t_cellarray.v
t_chg_first.v
t_clk_2in.v
t_clk_condflop_nord.v
t_clk_condflop.v
t_clk_dpulse.v
t_clk_dsp.v
t_clk_first.v
t_clk_gate_ext.v
t_clk_gen.v
t_clk_latch.v
t_clk_latchgate.v
t_clk_powerdn.v
t_clocker.v
t_concat_large.v
t_concat_opt.v
t_concat_sel.v
t_const.v
t_crazy_sel.v
t_EXAMPLE.v
t_fork_bbox.v
t_fork_label.v
t_func_endian.v
t_func_first.v
t_func_flip.v	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
t_func_gen.v
t_func_grey.v
t_func_lib.v
t_func_mlog2.v
t_func_numones.v
t_func_outfirst.v
t_func_outp.v
t_func_paramed.v
t_func_plog.v
t_func_range.v
t_func_real_param.v
t_func_regfirst.v
t_func_under2.v
t_func_under.v	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
t_func_uninit.v
t_func_wide.v	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
t_gate_elim.v
t_gate_lvalue_const.v
t_gated_clk_1.v
t_gen_alw.v
t_gen_cond_bitrange.v
t_gen_cond_const.v
t_gen_div0.v
t_gen_for0.v
t_gen_for1.v
t_gen_for_interface.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_gen_for_overlap.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_gen_for_shuffle.v
t_gen_for.v
t_gen_inc.v
t_gen_index.v
t_gen_intdot2.v
t_gen_local.v
t_inside_wild.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_inst_dff.v
t_inst_mism.v
t_inst_missing.v
t_inst_mnpipe.v
t_inst_port_array.v
t_inst_prepost.v
t_inst_signed1.v
t_inst_signed.v
t_inst_slice_part_select.v
t_inst_slice.v
t_inst_tree.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_interface1_modport.v
t_interface1.v
t_interface_ar2a.v
t_interface_ar2b.v
t_interface_gen4.v
t_interface_gen5.v
t_interface_gen6.v
t_interface_gen12.v
t_interface_gen.v
t_interface_modport_import.v
t_interface_modportlist.v
t_interface_param1.v
t_interface_parameter_access.v
t_interface_twod.v
t_langext_1.v
t_langext_2.v
t_langext_3.v
t_math_arith.v
t_math_concat0.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_math_cond_clean.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_math_const.v
t_math_divw.v
t_math_eq.v
t_math_imm2.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_math_imm.v
t_math_mul.v
t_math_real_public.v
t_math_reverse.v
t_math_shift_extend.v
t_math_shift_sel.v
t_math_sign_extend.v
t_math_signed2.v
t_math_signed3.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_math_signed4.v
t_math_signed6.v
t_math_signed7.v
t_math_signed_wire.v
t_math_strwidth.v
t_math_svl2.v
t_math_swap.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_math_tri.v
t_math_width.v
t_math_yosys.v
t_mem_banks.v
t_mem_cond.v
t_mem_func.v
t_mem_iforder.v
t_mem_multi_io2.v
t_mem_multi_io.v
t_mem_packed_assign.v
t_mem_shift.v
t_mem_slice.v
t_mem_slot.v
t_mem_twoedge.v
t_mem.v
t_mod_dup_ign.v
t_mod_interface_array0.v
t_mod_interface_array1.v
t_mod_interface_array2.v
t_mod_recurse1.v
t_mod_uselib.v
t_multitop1s.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_multitop_sig.v
t_opt_table_enum.v
t_opt_table_packed_array.v
t_opt_table_same.v
t_opt_table_signed.v
t_opt_table_sparse.v
t_optm_if_array.v
t_optm_if_cond.v
t_optm_redor.v
t_order_2d.v
t_order_a.v
t_order_b.v
t_order_clkinst.v
t_order_comboclkloop.v
t_order_doubleloop.v
t_order_first.v
t_order_multialways.v
t_order_multidriven.v
t_order_quad.v
t_order_wireloop.v
t_param_array2.v
t_param_array3.v
t_param_array4.v
t_param_array.v
t_param_avec.v
t_param_bit_sel.v
t_param_bracket.v
t_param_ceil.v
t_param_chain.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_param_const_part.v
t_param_ddeep_width.v
t_param_default.v
t_param_first_b.v
t_param_func2.v
t_param_func.v
t_param_if_blk.v
t_param_local.v
t_param_mem_attr.v
t_param_module.v
t_param_no_parentheses.v
t_param_package.v
t_param_real2.v
t_param_real.v
t_param_repl.v
t_param_seg.v
t_param_sel.v
t_param_shift.v
t_param_type2.v
t_param_type3.v
t_param_type.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_param_unreachable.v
t_param_value.v
t_param_while.v
t_param_wide_io.v
t_param_width.v
t_param.v
t_parse_delay.v
t_past_funcs.v
t_past.v
t_pp_display.v
t_pp_pragmas.v
t_real_param.v
t_reloop_offset.v
t_rnd.v
t_runflag.v
t_sc_names.v
t_select_2d.v
t_select_bound1.v
t_select_bound2.v
t_select_index2.v
t_select_index.v
t_select_lhs_oob2.v
t_select_lhs_oob.v
t_select_little_pack.v
t_select_param.v
t_select_plus_mul_pow2.v
t_select_runtime_range.v
t_select_set.v
t_slice_cond.v
t_slice_init.v
t_static_elab.v
t_table_fsm.v
t_time_literals.v
t_tri_array_bufif.v
t_tri_array_pull.v
t_tri_eqcase.v
t_tri_gen.v
t_tri_graph.v
t_tri_ifbegin.v
t_tri_inout2.v
t_tri_inout.v
t_tri_inz.v
t_tri_pull01.v
t_tri_pullup.v
t_tri_select_unsized.v
t_tri_select.v
t_tri_unconn.v
t_tri_various.v
t_type_param.v
t_type.v
t_unbounded.v
t_unconnected.v
t_uniqueif.v
t_unopt_array.v
t_unopt_combo.v
t_unopt_converge_initial.v
t_unopt_converge.v
t_unoptflat_simple_2.v
t_unoptflat_simple_3.v
t_unoptflat_simple.v
t_unpacked_slice.v
t_unroll_genf.v
t_vams_basic.v
t_var_const.v
t_var_dup2.v
t_var_dup3.v
t_var_in_assign.v
t_var_init.v
t_var_life.v
t_var_local.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_var_nonamebegin.v
t_var_overcmp.v
t_var_overzero.v
t_var_set_link.v
t_var_tieout.v
t_var_types.v
t_var_vec_sel.v
t_var_xref_gen.v	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
t_waiveroutput.v
t_wire_types.v
t_x_assign.v