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52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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parameter [31:0] TWENTY4 = 24;
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parameter [31:0] PA = TWENTY4/8;
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parameter [1:0] VALUE = 2'b10;
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parameter [5:0] REPL = {PA{VALUE}};
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parameter [7:0] CONC = {REPL,VALUE};
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parameter DBITS = 32;
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parameter INIT_BYTE = 8'h1F;
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parameter DWORDS_LOG2 = 7;
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parameter DWORDS = (1<<DWORDS_LOG2);
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parameter DBYTES=DBITS/8;
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// verilator lint_off LITENDIAN
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reg [DBITS-1:0] mem [0:DWORDS-1];
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// verilator lint_on LITENDIAN
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integer i;
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integer cyc=1;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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if (REPL != {2'b10,2'b10,2'b10}) $stop;
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if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop;
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end
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if (cyc==2) begin
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for (i = 0; i < DWORDS; i = i + 1)
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mem[i] = {DBYTES{INIT_BYTE}};
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end
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if (cyc==3) begin
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for (i = 0; i < DWORDS; i = i + 1)
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if (mem[i] != {DBYTES{INIT_BYTE}}) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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