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23 lines
662 B
Verilog
23 lines
662 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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initial begin
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// verilator lint_off WIDTH
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if (32'hxxxxxxxx !== 'hx) $stop;
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if (32'hzzzzzzzz !== 'hz) $stop;
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if (32'h???????? !== 'h?) $stop;
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if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop;
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if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop;
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if (68'h?_????????_???????? !== 'd?) $stop;
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// verilator lint_on WIDTH
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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