mirror of
https://github.com/sehugg/8bitworkshop.git
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150 lines
3.4 KiB
Verilog
150 lines
3.4 KiB
Verilog
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`include "hvsync_generator.v"
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`include "cpu16.v"
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// uncomment to see scope view
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//`define DEBUG
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module frame_buffer_top(clk, reset, hsync, vsync, hpaddle, vpaddle,
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address_bus, to_cpu, from_cpu, write_enable
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`ifdef DEBUG
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, output [15:0] IP
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, output carry
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, output zero
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`else
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, rgb
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`endif
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);
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input clk, reset;
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input hpaddle, vpaddle;
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output hsync, vsync;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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`ifdef DEBUG
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assign IP = cpu.regs[cpu.IP];
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assign carry = cpu.carry;
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assign zero = cpu.zero;
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`else
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output [3:0] rgb;
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`endif
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parameter IN_HPOS = 8'b01000000;
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parameter IN_VPOS = 8'b01000001;
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parameter IN_FLAGS = 8'b01000010;
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reg [15:0] ram[0:32767];
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reg [15:0] rom[0:1023];
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output wire [15:0] address_bus;
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output reg [15:0] to_cpu;
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output wire [15:0] from_cpu;
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output wire write_enable;
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CPU16 cpu(.clk(clk),
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.reset(reset),
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.hold(hold),
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.busy(busy),
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.address(address_bus),
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.data_in(to_cpu),
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.data_out(from_cpu),
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.write(write_enable));
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always @(posedge clk)
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if (write_enable) begin
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ram[address_bus[14:0]] <= from_cpu;
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end
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always @(*)
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if (address_bus[15])
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to_cpu = rom[address_bus[9:0]];
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else if (&address_bus[14:8]) begin
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casez (address_bus[7:0])
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// special read registers
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IN_HPOS: to_cpu = {8'b0, hpos[7:0]};
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IN_VPOS: to_cpu = {8'b0, vpos[7:0]};
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IN_FLAGS: to_cpu = {11'b0,
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vsync, hsync, vpaddle, hpaddle, display_on};
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default: to_cpu = 0;
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endcase
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end else
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to_cpu = ram[address_bus[14:0]];
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(0),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// video DMA access
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reg hold;
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wire busy;
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reg [15:0] vline[0:31]; // 32x16 bits = 256 4-color pixels
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reg [4:0] vindex; // index into line array
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reg [15:0] vshift; // shift register with current word to output
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reg [3:0] palette[0:3] = '{0,1,4,7}; // simple palette
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always @(posedge clk) begin
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// has CPU released the bus?
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if (busy) begin
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// write from main RAM -> scanline RAM
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vline[vindex] <= ram[{2'b10,vpos[7:0],vindex}];
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// end of scanline read?
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if (&vindex)
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hold <= 0; // release CPU
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vindex <= vindex + 1; // next address
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end else if (hpos >= 256 && hpos < 256+4 && vpos < 240) begin
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hold <= 1; // start DMA mode, hold CPU
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end else if (!hpos[8] && vpos < 240) begin
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// load next word from vline buffer
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if (0 == hpos[2:0]) begin
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vshift <= vline[vindex];
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vindex <= vindex + 1;
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end else
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vshift <= vshift >> 2;
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// decode scanline RAM to RGB output
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rgb <= palette[vshift[1:0]];
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end else
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rgb <= 0;
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end
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`ifdef EXT_INLINE_ASM
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initial begin
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rom = '{
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__asm
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.arch femto16
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.org 32768
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.len 1024
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.define IN_HPOS $7f00
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.define IN_VPOS $7f01
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.define IN_FLAGS $7f02
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.define F_DISPLAY 1
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.define F_HPADDLE 2
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.define F_VPADDLE 4
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.define F_HSYNC 8
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.define F_VSYNC 16
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Start:
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mov ax,#0
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mov bx,ax
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Loop:
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xor ax,[bx]
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mov [bx],ax
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inc bx
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inc ax
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bnz Loop
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reset
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__endasm
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};
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end
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`endif
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endmodule
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