mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-27 01:51:35 +00:00
676 lines
13 KiB
Verilog
676 lines
13 KiB
Verilog
`define NTSC 1
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/* for Silice: https://github.com/sylefeb/Silice */
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`define VERILATOR 1
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`define COLOR_DEPTH 8
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/*verilator lint_off pinmissing */
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/*verilator lint_off undriven */
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/*verilator lint_off width */
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`timescale 1ns / 1ps
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`default_nettype none
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module top(
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`ifdef NTSC
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// NTSC
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output reg [31:0] rgb,
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output hsync,
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output vsync,
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`endif
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input clk,
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input reset
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);
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wire [7:0] __main_video_r;
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wire [7:0] __main_video_g;
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wire [7:0] __main_video_b;
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wire __main_video_hs;
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wire __main_video_vs;
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// main
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wire run_main;
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assign run_main = 1'b1;
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wire done_main;
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M_main __main(
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.clock(clk),
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.reset(reset),
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`ifdef NTSC
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.out_video_r(__main_video_r),
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.out_video_g(__main_video_g),
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.out_video_b(__main_video_b),
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.out_video_hs(__main_video_hs),
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.out_video_vs(__main_video_vs),
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`endif
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.in_run(run_main),
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.out_done(done_main)
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);
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assign rgb = {8'hff, __main_video_b, __main_video_g, __main_video_r};
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assign hsync = __main_video_hs;
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assign vsync = __main_video_vs;
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endmodule
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module M_ntsc (
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out_ntsc_hs,
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out_ntsc_vs,
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out_active,
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out_vblank,
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out_ntsc_x,
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out_ntsc_y,
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in_run,
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out_done,
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reset,
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out_clock,
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clock
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);
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output [0:0] out_ntsc_hs;
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output [0:0] out_ntsc_vs;
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output [0:0] out_active;
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output [0:0] out_vblank;
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output [9:0] out_ntsc_x;
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output [9:0] out_ntsc_y;
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input in_run;
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output out_done;
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input reset;
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output out_clock;
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input clock;
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assign out_clock = clock;
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wire [9:0] _c_H_FRT_PORCH;
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assign _c_H_FRT_PORCH = 7;
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wire [9:0] _c_H_SYNCH;
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assign _c_H_SYNCH = 23;
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wire [9:0] _c_H_BCK_PORCH;
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assign _c_H_BCK_PORCH = 23;
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wire [9:0] _c_H_RES;
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assign _c_H_RES = 256;
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wire [9:0] _c_V_FRT_PORCH;
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assign _c_V_FRT_PORCH = 5;
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wire [9:0] _c_V_SYNCH;
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assign _c_V_SYNCH = 3;
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wire [9:0] _c_V_BCK_PORCH;
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assign _c_V_BCK_PORCH = 14;
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wire [9:0] _c_V_RES;
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assign _c_V_RES = 240;
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reg [9:0] _t_HS_START;
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reg [9:0] _t_HS_END;
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reg [9:0] _t_HA_START;
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reg [9:0] _t_H_END;
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reg [9:0] _t_VS_START;
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reg [9:0] _t_VS_END;
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reg [9:0] _t_VA_START;
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reg [9:0] _t_V_END;
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reg [9:0] _d_xcount;
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reg [9:0] _q_xcount;
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reg [9:0] _d_ycount;
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reg [9:0] _q_ycount;
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reg [0:0] _d_ntsc_hs,_q_ntsc_hs;
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reg [0:0] _d_ntsc_vs,_q_ntsc_vs;
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reg [0:0] _d_active,_q_active;
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reg [0:0] _d_vblank,_q_vblank;
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reg [9:0] _d_ntsc_x,_q_ntsc_x;
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reg [9:0] _d_ntsc_y,_q_ntsc_y;
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reg [1:0] _d_index,_q_index;
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assign out_ntsc_hs = _d_ntsc_hs;
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assign out_ntsc_vs = _d_ntsc_vs;
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assign out_active = _d_active;
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assign out_vblank = _d_vblank;
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assign out_ntsc_x = _d_ntsc_x;
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assign out_ntsc_y = _d_ntsc_y;
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assign out_done = (_q_index == 3);
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always @(posedge clock) begin
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if (reset || !in_run) begin
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_q_xcount <= 0;
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_q_ycount <= 0;
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if (reset) begin
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_q_index <= 0;
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end else begin
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_q_index <= 0;
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end
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end else begin
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_q_xcount <= _d_xcount;
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_q_ycount <= _d_ycount;
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_q_ntsc_hs <= _d_ntsc_hs;
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_q_ntsc_vs <= _d_ntsc_vs;
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_q_active <= _d_active;
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_q_vblank <= _d_vblank;
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_q_ntsc_x <= _d_ntsc_x;
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_q_ntsc_y <= _d_ntsc_y;
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_q_index <= _d_index;
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end
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end
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always @* begin
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_d_xcount = _q_xcount;
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_d_ycount = _q_ycount;
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_d_ntsc_hs = _q_ntsc_hs;
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_d_ntsc_vs = _q_ntsc_vs;
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_d_active = _q_active;
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_d_vblank = _q_vblank;
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_d_ntsc_x = _q_ntsc_x;
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_d_ntsc_y = _q_ntsc_y;
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_d_index = _q_index;
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_t_HS_START = 0;
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_t_HS_END = 0;
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_t_HA_START = 0;
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_t_H_END = 0;
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_t_VS_START = 0;
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_t_VS_END = 0;
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_t_VA_START = 0;
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_t_V_END = 0;
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// _always_pre
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_t_HS_START = _c_H_FRT_PORCH;
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_t_HS_END = _c_H_FRT_PORCH+_c_H_SYNCH;
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_t_HA_START = _c_H_FRT_PORCH+_c_H_SYNCH+_c_H_BCK_PORCH;
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_t_H_END = _c_H_FRT_PORCH+_c_H_SYNCH+_c_H_BCK_PORCH+_c_H_RES;
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_t_VS_START = _c_V_FRT_PORCH;
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_t_VS_END = _c_V_FRT_PORCH+_c_V_SYNCH;
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_t_VA_START = _c_V_FRT_PORCH+_c_V_SYNCH+_c_V_BCK_PORCH;
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_t_V_END = _c_V_FRT_PORCH+_c_V_SYNCH+_c_V_BCK_PORCH+_c_V_RES;
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_d_ntsc_hs = ((_q_xcount>=_t_HS_START&&_q_xcount<_t_HS_END));
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_d_ntsc_vs = ((_q_ycount>=_t_VS_START&&_q_ycount<_t_VS_END));
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_d_active = (_q_xcount>=_t_HA_START&&_q_xcount<_t_H_END)&&(_q_ycount>=_t_VA_START&&_q_ycount<_t_V_END);
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_d_vblank = (_q_ycount<_t_VA_START);
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_d_index = 3;
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(* full_case *)
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case (_q_index)
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0: begin
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// _top
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// var inits
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_t_HS_START = 0;
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_t_HS_END = 0;
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_t_HA_START = 0;
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_t_H_END = 0;
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_t_VS_START = 0;
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_t_VS_END = 0;
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_t_VA_START = 0;
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_t_V_END = 0;
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_d_xcount = 0;
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_d_ycount = 0;
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// --
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_d_xcount = 0;
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_d_ycount = 0;
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_d_index = 1;
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end
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1: begin
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// __while__block_1
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if (1) begin
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// __block_2
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// __block_4
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_d_ntsc_x = (_d_active)?_q_xcount-_t_HA_START:0;
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_d_ntsc_y = (_d_vblank)?0:_q_ycount-_t_VA_START;
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if (_q_xcount==_t_H_END-1) begin
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// __block_5
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// __block_7
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_d_xcount = 0;
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if (_q_ycount==_t_V_END-1) begin
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// __block_8
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// __block_10
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_d_ycount = 0;
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// __block_11
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end else begin
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// __block_9
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// __block_12
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_d_ycount = _q_ycount+1;
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// __block_13
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end
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// __block_14
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// __block_15
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end else begin
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// __block_6
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// __block_16
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_d_xcount = _q_xcount+1;
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// __block_17
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end
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// __block_18
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// __block_19
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_d_index = 1;
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end else begin
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_d_index = 2;
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end
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end
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2: begin
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// __block_3
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_d_index = 3;
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end
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3: begin // end of ntsc
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end
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default: begin
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_d_index = 3;
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end
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endcase
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end
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endmodule
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module M_frame_display (
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in_pix_x,
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in_pix_y,
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in_pix_active,
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in_pix_vblank,
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out_pix_r,
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out_pix_g,
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out_pix_b,
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in_run,
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out_done,
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reset,
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out_clock,
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clock
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);
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input [9:0] in_pix_x;
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input [9:0] in_pix_y;
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input [0:0] in_pix_active;
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input [0:0] in_pix_vblank;
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output [7:0] out_pix_r;
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output [7:0] out_pix_g;
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output [7:0] out_pix_b;
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input in_run;
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output out_done;
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input reset;
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output out_clock;
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input clock;
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assign out_clock = clock;
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wire [6:0] _c_wave[63:0];
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assign _c_wave[0] = 0;
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assign _c_wave[1] = 0;
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assign _c_wave[2] = 1;
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assign _c_wave[3] = 2;
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assign _c_wave[4] = 4;
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assign _c_wave[5] = 7;
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assign _c_wave[6] = 11;
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assign _c_wave[7] = 14;
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assign _c_wave[8] = 19;
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assign _c_wave[9] = 23;
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assign _c_wave[10] = 29;
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assign _c_wave[11] = 34;
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assign _c_wave[12] = 40;
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assign _c_wave[13] = 46;
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assign _c_wave[14] = 52;
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assign _c_wave[15] = 58;
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assign _c_wave[16] = 65;
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assign _c_wave[17] = 71;
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assign _c_wave[18] = 77;
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assign _c_wave[19] = 83;
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assign _c_wave[20] = 89;
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assign _c_wave[21] = 95;
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assign _c_wave[22] = 100;
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assign _c_wave[23] = 105;
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assign _c_wave[24] = 110;
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assign _c_wave[25] = 114;
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assign _c_wave[26] = 117;
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assign _c_wave[27] = 120;
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assign _c_wave[28] = 123;
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assign _c_wave[29] = 125;
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assign _c_wave[30] = 126;
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assign _c_wave[31] = 126;
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assign _c_wave[32] = 126;
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assign _c_wave[33] = 126;
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assign _c_wave[34] = 125;
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assign _c_wave[35] = 123;
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assign _c_wave[36] = 120;
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assign _c_wave[37] = 117;
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assign _c_wave[38] = 114;
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assign _c_wave[39] = 110;
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assign _c_wave[40] = 105;
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assign _c_wave[41] = 100;
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assign _c_wave[42] = 95;
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assign _c_wave[43] = 89;
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assign _c_wave[44] = 83;
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assign _c_wave[45] = 77;
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assign _c_wave[46] = 71;
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assign _c_wave[47] = 65;
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assign _c_wave[48] = 58;
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assign _c_wave[49] = 52;
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assign _c_wave[50] = 46;
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assign _c_wave[51] = 40;
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assign _c_wave[52] = 34;
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assign _c_wave[53] = 29;
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assign _c_wave[54] = 23;
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assign _c_wave[55] = 19;
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assign _c_wave[56] = 14;
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assign _c_wave[57] = 11;
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assign _c_wave[58] = 7;
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assign _c_wave[59] = 4;
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assign _c_wave[60] = 2;
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assign _c_wave[61] = 1;
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assign _c_wave[62] = 0;
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assign _c_wave[63] = 0;
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reg [7:0] _t_v;
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reg [5:0] _d_frame;
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reg [5:0] _q_frame;
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reg signed [8:0] _d_pos[3:0];
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reg signed [8:0] _q_pos[3:0];
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reg [7:0] _d_pix_r,_q_pix_r;
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reg [7:0] _d_pix_g,_q_pix_g;
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reg [7:0] _d_pix_b,_q_pix_b;
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reg [2:0] _d_index,_q_index;
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assign out_pix_r = _d_pix_r;
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assign out_pix_g = _d_pix_g;
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assign out_pix_b = _d_pix_b;
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assign out_done = (_q_index == 6);
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always @(posedge clock) begin
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if (reset || !in_run) begin
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_q_frame <= 0;
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_q_pos[0] <= 0;
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_q_pos[1] <= 0;
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_q_pos[2] <= 0;
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_q_pos[3] <= 0;
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if (reset) begin
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_q_index <= 0;
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end else begin
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_q_index <= 0;
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end
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end else begin
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_q_frame <= _d_frame;
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_q_pos[0] <= _d_pos[0];
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_q_pos[1] <= _d_pos[1];
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_q_pos[2] <= _d_pos[2];
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_q_pos[3] <= _d_pos[3];
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_q_pix_r <= _d_pix_r;
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_q_pix_g <= _d_pix_g;
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_q_pix_b <= _d_pix_b;
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_q_index <= _d_index;
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end
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end
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always @* begin
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_d_frame = _q_frame;
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_d_pos[0] = _q_pos[0];
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_d_pos[1] = _q_pos[1];
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_d_pos[2] = _q_pos[2];
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_d_pos[3] = _q_pos[3];
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_d_pix_r = _q_pix_r;
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_d_pix_g = _q_pix_g;
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_d_pix_b = _q_pix_b;
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_d_index = _q_index;
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_t_v = 0;
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// _always_pre
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_d_pix_r = 0;
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_d_pix_g = 0;
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_d_pix_b = 0;
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_d_index = 6;
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(* full_case *)
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case (_q_index)
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0: begin
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// _top
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// var inits
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_t_v = 0;
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_d_frame = 0;
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_d_pos[0] = 0;
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_d_pos[1] = 0;
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_d_pos[2] = 0;
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_d_pos[3] = 0;
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// --
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_d_index = 1;
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end
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1: begin
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// __while__block_1
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if (1) begin
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// __block_2
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// __block_4
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_d_index = 3;
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end else begin
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_d_index = 2;
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end
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end
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3: begin
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// __while__block_5
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if (in_pix_vblank==0) begin
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// __block_6
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// __block_8
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if (in_pix_active) begin
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// __block_9
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// __block_11
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if (in_pix_y+20>_q_pos[0]&&in_pix_y<_q_pos[0]+20) begin
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// __block_12
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// __block_14
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_t_v = ((_c_wave[in_pix_y-_q_pos[0]+32]>>1)*(0+5))>>3;
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_d_pix_r = _t_v*4;
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_d_pix_g = _t_v*3;
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_d_pix_b = _t_v*2;
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// __block_15
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end else begin
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// __block_13
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end
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// __block_16
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if (in_pix_y+20>_q_pos[1]&&in_pix_y<_q_pos[1]+20) begin
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// __block_17
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// __block_19
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_t_v = ((_c_wave[in_pix_y-_q_pos[1]+32]>>1)*(1+5))>>3;
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_d_pix_r = _t_v*4;
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_d_pix_g = _t_v*3;
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_d_pix_b = _t_v*2;
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// __block_20
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end else begin
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// __block_18
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end
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// __block_21
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if (in_pix_y+20>_q_pos[2]&&in_pix_y<_q_pos[2]+20) begin
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// __block_22
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// __block_24
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_t_v = ((_c_wave[in_pix_y-_q_pos[2]+32]>>1)*(2+5))>>3;
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_d_pix_r = _t_v*4;
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_d_pix_g = _t_v*3;
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_d_pix_b = _t_v*2;
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// __block_25
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end else begin
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// __block_23
|
|
end
|
|
// __block_26
|
|
if (in_pix_y+20>_q_pos[3]&&in_pix_y<_q_pos[3]+20) begin
|
|
// __block_27
|
|
// __block_29
|
|
_t_v = ((_c_wave[in_pix_y-_q_pos[3]+32]>>1)*(3+5))>>3;
|
|
_d_pix_r = _t_v*4;
|
|
_d_pix_g = _t_v*3;
|
|
_d_pix_b = _t_v*2;
|
|
// __block_30
|
|
end else begin
|
|
// __block_28
|
|
end
|
|
// __block_31
|
|
// __block_32
|
|
end else begin
|
|
// __block_10
|
|
end
|
|
// __block_33
|
|
// __block_34
|
|
_d_index = 3;
|
|
end else begin
|
|
_d_index = 4;
|
|
end
|
|
end
|
|
2: begin
|
|
// __block_3
|
|
_d_index = 6;
|
|
end
|
|
4: begin
|
|
// __block_7
|
|
_d_frame = _q_frame+1;
|
|
_d_pos[0] = 113+(_c_wave[(_d_frame+(0<<3))&63]<<1);
|
|
_d_pos[1] = 113+(_c_wave[(_d_frame+(1<<3))&63]<<1);
|
|
_d_pos[2] = 113+(_c_wave[(_d_frame+(2<<3))&63]<<1);
|
|
_d_pos[3] = 113+(_c_wave[(_d_frame+(3<<3))&63]<<1);
|
|
_d_index = 5;
|
|
end
|
|
5: begin
|
|
// __while__block_35
|
|
if (in_pix_vblank==1) begin
|
|
// __block_36
|
|
// __block_38
|
|
// __block_39
|
|
_d_index = 5;
|
|
end else begin
|
|
_d_index = 1;
|
|
end
|
|
end
|
|
6: begin // end of frame_display
|
|
end
|
|
default: begin
|
|
_d_index = 6;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|
|
|
|
|
|
module M_main (
|
|
out_video_r,
|
|
out_video_g,
|
|
out_video_b,
|
|
out_video_hs,
|
|
out_video_vs,
|
|
in_run,
|
|
out_done,
|
|
reset,
|
|
out_clock,
|
|
clock
|
|
);
|
|
output [7:0] out_video_r;
|
|
output [7:0] out_video_g;
|
|
output [7:0] out_video_b;
|
|
output [0:0] out_video_hs;
|
|
output [0:0] out_video_vs;
|
|
input in_run;
|
|
output out_done;
|
|
input reset;
|
|
output out_clock;
|
|
input clock;
|
|
assign out_clock = clock;
|
|
wire [0:0] _w_ntsc_driver_ntsc_hs;
|
|
wire [0:0] _w_ntsc_driver_ntsc_vs;
|
|
wire [0:0] _w_ntsc_driver_active;
|
|
wire [0:0] _w_ntsc_driver_vblank;
|
|
wire [9:0] _w_ntsc_driver_ntsc_x;
|
|
wire [9:0] _w_ntsc_driver_ntsc_y;
|
|
wire _w_ntsc_driver_done;
|
|
wire [7:0] _w_display_pix_r;
|
|
wire [7:0] _w_display_pix_g;
|
|
wire [7:0] _w_display_pix_b;
|
|
wire _w_display_done;
|
|
|
|
reg [7:0] _d_frame;
|
|
reg [7:0] _q_frame;
|
|
reg [2:0] _d_index,_q_index;
|
|
reg _ntsc_driver_run;
|
|
reg _display_run;
|
|
assign out_video_r = _w_display_pix_r;
|
|
assign out_video_g = _w_display_pix_g;
|
|
assign out_video_b = _w_display_pix_b;
|
|
assign out_video_hs = _w_ntsc_driver_ntsc_hs;
|
|
assign out_video_vs = _w_ntsc_driver_ntsc_vs;
|
|
assign out_done = (_q_index == 5);
|
|
|
|
always @(posedge clock) begin
|
|
if (reset || !in_run) begin
|
|
_q_frame <= 0;
|
|
if (reset) begin
|
|
_q_index <= 0;
|
|
end else begin
|
|
_q_index <= 0;
|
|
end
|
|
end else begin
|
|
_q_frame <= _d_frame;
|
|
_q_index <= _d_index;
|
|
end
|
|
end
|
|
|
|
M_ntsc ntsc_driver (
|
|
.out_ntsc_hs(_w_ntsc_driver_ntsc_hs),
|
|
.out_ntsc_vs(_w_ntsc_driver_ntsc_vs),
|
|
.out_active(_w_ntsc_driver_active),
|
|
.out_vblank(_w_ntsc_driver_vblank),
|
|
.out_ntsc_x(_w_ntsc_driver_ntsc_x),
|
|
.out_ntsc_y(_w_ntsc_driver_ntsc_y),
|
|
.out_done(_w_ntsc_driver_done),
|
|
.in_run(_ntsc_driver_run),
|
|
.reset(reset),
|
|
.clock(clock)
|
|
);
|
|
M_frame_display display (
|
|
.in_pix_x(_w_ntsc_driver_ntsc_x),
|
|
.in_pix_y(_w_ntsc_driver_ntsc_y),
|
|
.in_pix_active(_w_ntsc_driver_active),
|
|
.in_pix_vblank(_w_ntsc_driver_vblank),
|
|
.out_pix_r(_w_display_pix_r),
|
|
.out_pix_g(_w_display_pix_g),
|
|
.out_pix_b(_w_display_pix_b),
|
|
.out_done(_w_display_done),
|
|
.in_run(_display_run),
|
|
.reset(reset),
|
|
.clock(clock)
|
|
);
|
|
|
|
|
|
|
|
always @* begin
|
|
_d_frame = _q_frame;
|
|
_d_index = _q_index;
|
|
_ntsc_driver_run = 1;
|
|
_display_run = 1;
|
|
// _always_pre
|
|
_d_index = 5;
|
|
(* full_case *)
|
|
case (_q_index)
|
|
0: begin
|
|
// _top
|
|
// var inits
|
|
_d_frame = 0;
|
|
// --
|
|
_d_index = 1;
|
|
end
|
|
1: begin
|
|
// __while__block_1
|
|
if (1) begin
|
|
// __block_2
|
|
// __block_4
|
|
_d_index = 3;
|
|
end else begin
|
|
_d_index = 2;
|
|
end
|
|
end
|
|
3: begin
|
|
// __while__block_5
|
|
if (_w_ntsc_driver_vblank==0) begin
|
|
// __block_6
|
|
// __block_8
|
|
// __block_9
|
|
_d_index = 3;
|
|
end else begin
|
|
_d_index = 4;
|
|
end
|
|
end
|
|
2: begin
|
|
// __block_3
|
|
_d_index = 5;
|
|
end
|
|
4: begin
|
|
// __block_7
|
|
_d_frame = _q_frame+1;
|
|
// __block_10
|
|
_d_index = 1;
|
|
end
|
|
5: begin // end of main
|
|
end
|
|
default: begin
|
|
_d_index = 5;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|
|
|