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46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg alu_ltu, alu_lts;
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logic [3:0] in_op1;
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logic [3:0] in_op2;
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reg aaa_ltu, aaa_lts;
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always @(posedge clk) begin
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in_op1 = 4'sb1110;
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in_op2 = 4'b0010;
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aaa_ltu = in_op1 < in_op2;
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// bug999
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aaa_lts = $signed(in_op1) < $signed(in_op2);
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`checkh (aaa_ltu, 1'b0);
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`checkh (aaa_lts, 1'b1);
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end
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generate if (1) begin
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always @(posedge clk) begin
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in_op1 = 4'sb1110;
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in_op2 = 4'b0010;
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alu_ltu = in_op1 < in_op2;
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// bug999
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alu_lts = $signed(in_op1) < $signed(in_op2);
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`checkh (alu_ltu, 1'b0);
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`checkh (alu_lts, 1'b1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endgenerate
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endmodule
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