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94 lines
2.0 KiB
Verilog
94 lines
2.0 KiB
Verilog
`include "hvsync_generator.v"
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module seven_segment_decoder(digit, segments);
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input [3:0] digit;
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output [6:0] segments;
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always @(*)
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case(digit)
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0: segments = 7'b1111110;
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1: segments = 7'b0110000;
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2: segments = 7'b1101101;
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3: segments = 7'b1111001;
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4: segments = 7'b0110011;
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5: segments = 7'b1011011;
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6: segments = 7'b1011111;
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7: segments = 7'b1110000;
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8: segments = 7'b1111111;
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9: segments = 7'b1111011;
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default: segments = 7'b0000000;
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endcase
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endmodule
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module segments_to_bitmap(segments, line, bits);
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input [6:0] segments;
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input [2:0] line;
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output [4:0] bits;
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always @(*)
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case (line)
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0:bits = (segments[6]?5'b11111:0)
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^ (segments[5]?5'b00001:0)
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^ (segments[1]?5'b10000:0);
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1:bits = (segments[1]?5'b10000:0)
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^ (segments[5]?5'b00001:0);
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2:bits = (segments[0]?5'b11111:0)
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^ (|segments[5:4]?5'b00001:0)
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^ (|segments[2:1]?5'b10000:0);
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3:bits = (segments[2]?5'b10000:0)
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^ (segments[4]?5'b00001:0);
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4:bits = (segments[3]?5'b11111:0)
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^ (segments[4]?5'b00001:0)
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^ (segments[2]?5'b10000:0);
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default:bits = 0;
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endcase
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endmodule
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module test_numbers_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [3:0] digit = hpos[7:4];
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wire [2:0] xofs = hpos[3:1];
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wire [2:0] yofs = vpos[3:1];
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wire [4:0] bits;
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wire [6:0] segments;
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seven_segment_decoder decoder(
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.digit(digit),
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.segments(segments)
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);
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segments_to_bitmap numbers(
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.segments(segments),
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.line(yofs),
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.bits(bits)
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);
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wire r = display_on && 0;
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wire g = display_on && bits[~xofs];
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wire b = display_on && 0;
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assign rgb = {b,g,r};
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endmodule
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