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53 lines
1021 B
Verilog
53 lines
1021 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg signed i;
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wire signed o1;
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wire signed o2;
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integer cyc; initial cyc=0;
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sub1 sub1 (.i(i), .o(o1));
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sub2 sub2 (.i(o1), .o(o2));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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i <= 1'b0;
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end
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else if (cyc==1) begin
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if (o2 != 1'b0) $stop;
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i <= 1'b1;
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end
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else if (cyc==2) begin
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if (o2 != 1'b1) $stop;
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end
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if (cyc==3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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//msg2540
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module sub1 (
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input signed i,
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output wire signed o);
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assign o = ~i;
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endmodule
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module sub2 (i,o);
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input signed i;
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output signed o;
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wire signed o = ~i;
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endmodule
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